Method of testing switches and switching circuit
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYoshio Matsuda, Harufusa Kondoh, Isamu Hayashi, Hiromi Notani
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYoshio Matsuda, Harufusa Kondoh, Isamu Hayashi, Hiromi Notani
Estimating the term…
Incoming lines (I0 to I7) are connected to a space switch (2) through input data latches (1). The space switch (2) is connected to a normal/test changeover switch (12), which is connected to a normal/test changeover switch (13) through serial-to-parallel converting circuits (3), common buffer memories (4) and parallel-to-serial converting circuits (5). Space switches (6) are connected to the normal/test changeover switch (13). Outgoing lines (O0 to O7) are connected to the space switches 6 through output data latches (8). Connection states in the switches (2, 6) are placed in transposed relation to each other by a transposed connection generating circuit (10) in a test operation, so that the switches (2, 6) are directly connected to each other through the switches (12, 13). Predetermined data applied to the incoming lines are intactly used as expected values for judgement of the normal or abnormal operation of the set of switches of matrix structure.
A method of testing switches of a signal transmission system including a signal processor for performing a predetermined processing upon receipt of a plurality of inputs in predetermined number to provide outputs in the same number as said predetermined number, a first switch of matrix structure for performing a first predetermined exchange before said predetermined processing, and a second switch of matrix structure for performing a second predetermined exchange after said predetermined processing, said method comprising the steps of:
A switching circuit comprising:
Dependencies are inferred from the claim text.