# US 5,347,185 A · Protection structure against latch-up in a CMOS circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,347,185 A - Document ID: US5347185A - Status: Granted - Kind: A - Application number: 07/892,941 - Filed: 1992-06-03 - Granted: 1994-09-13 - Earliest claimed: 1992-06-03 - Assignees: SGS-Thomson Microelectronics S.A. - Inventors: Francois Tailliet - Web page: https://patentgrep.com/patent/US5347185A ## CPC - H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A CMOS circuit protected against latch-up. A limiter parallel to the internal circuitry of the CMOS circuit increases the external current for the triggering of the latch-up in the event of overvoltage on the supply. In one embodiment, the parallel limiter is intrinsically protected against electrostatic discharges. In another embodiment, the limiter is protected by a series connected resistor and a separate shunt-connected ESD protection structure. ## Claims ### Claim 1 A CMOS circuit protected against latch-up, comprising: internal circuitry connected between a first more positive supply terminal and a second more negative supply terminal to draw power therefrom, said internal circuitry having, as known parameters, a current I.sub.1 and a voltage V.sub.1 for the triggering of the latch-up phenomenon; a limiter, connected, in parallel with the internal circuitry, between the first supply terminal and the second supply terminal, this limiter having a triggering threshold below voltage V.sub.1 and consuming current of a value far higher than I.sub.1 when a voltage of V.sub.1 or greater is applied between the first and second supply terminals. ### Claim 2 (depends on 1) A CMOS circuit according to claim 1, wherein the triggering threshold of said limiter is higher than a maximum voltage permitted for the operation of the CMOS internal circuitry. ### Claim 3 (depends on 1) A CMOS circuit according to claim 1, wherein said limiter comprises zener diodes that are operatively connected in series between the first supply terminal and the second supply terminal, the sum of the reverse-breakdown threshold voltages of the diodes being equal to the triggering threshold of said limiter. ### Claim 4 (depends on 1) A CMOS circuit according to claim 1, wherein said limiter comprises two zener diodes in series, each diode having a threshold of the order of 6 volts. ### Claim 5 (depends on 1) A CMOS circuit according to claim 1, further comprising a protection circuit against electrostatic discharges which is connected, in parallel with said limiter, between said first supply terminal and said second supply terminal. ### Claim 6 (depends on 1) A CMOS circuit according to claim 1, further comprising a protection resistor which is placed in series between said first supply terminal and said limiter. ### Claim 7 (depends on 1) A CMOS circuit according to claim 1, further comprising: a protection resistor which is placed in series between said first supply terminal and said limiter; and a lateral bipolar transistor, having a collector connected to said first supply terminal, and an emitter and a base connected to said second supply terminal. ### Claim 8 (depends on 1) A CMOS circuit according to claim 1, wherein said limiter is a lateral bipolar transistor, one collector of which is connected to said first supply terminal, and one emitter and one base of which is connected to said second supply terminal, and wherein said base has been overdoped to diminish a collector-base avalanche voltage. ### Claim 9 (depends on 1) The integrated circuit of claim 1, wherein said limiter has a threshold voltage in the range of about 10-15 V inclusive. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein said power supply connections are specified for connection for approximately 5 Volts of supply voltage, and said limiter has a threshold voltage of about 12 V. ### Claim 11 (depends on 1) The integrated circuit of claim 1, wherein said limiter has a dynamic on-resistance of no more than a few tens of ohms. ### Claim 12 (depends on 1) The integrated circuit of claim 1, wherein said limiter comprises multiple Zener diodes in series. ### Claim 13 A CMOS integrated circuit, comprising: first and second power supply input connections; a plurality of active devices connected to implement a desired circuit configuration, and operatively connected to be powered from said first and second power supply input connections, and configured to reliably withstand peak voltages of at least a specified value Vmax; a limiter circuit, having a nonlinear response with a low dynamic impedance R.sub.e at applied voltages greater than a threshold voltage E; said limiter being connected, in series with a resistance, between said first and second power supply connections; an electrostatic discharge protection device, connected directly between said first and second power supply connections, said electrostatic discharge protection device having a nonlinear response with a very low impedance at applied voltages greater than a threshold voltage Vo; wherein said limiter and said electrostatic discharge protection device have respective device parameters such that Vmax<E<Vo. ### Claim 14 (depends on 13) The integrated circuit of claim 13, wherein said limiter has a threshold voltage in the range of about 10-15 V inclusive. ### Claim 15 (depends on 13) The integrated circuit of claim 13, wherein said power supply connections are specified for connection to approximately 5 Volts of supply voltage, and said limiter has a threshold voltage of about 12 V. ### Claim 16 (depends on 13) The integrated circuit of claim 13, wherein said limiter has a dynamic on-resistance of no more than a few tens of ohms. ### Claim 17 (depends on 13) The integrated circuit of claim 13, wherein said limiter has a dynamic on-resistance of about 20 ohms. ### Claim 18 (depends on 13) The integrated circuit of claim 13, wherein said limiter comprises multiple Zener diodes in series. ### Claim 19 A CMOS integrated circuit, comprising: first and second power supply input connections; a plurality of active devices connected to implement a desired circuit configuration, and operatively connected to be powered from said first and second power supply input connections, and configured to reliably withstand peak voltages of at least a specified value Vmax; said plurality of active devices collectively having a latchup trigger voltage of least V1, and a latchup holding current of at least I1; a limiter circuit, comprising a Zener diode structure having a threshold voltage E; said limiter being connected, in series with a resistance, between said first and second power supply connections; an electrostatic discharge protection device, comprising a diode-connected bipolar transistor connected directly between said first and second power supply connections, said electrostatic discharge protection device having a threshold voltage Vo; wherein said limiter and said electrostatic discharge protection device have respective device parameters such that Vmax<E, E<V1, and E<Vo. ### Claim 20 (depends on 19) The integrated circuit of claim 19, wherein said limiter has a threshold voltage in the range of about 10-15 V inclusive. ### Claim 21 (depends on 19) The integrated circuit of claim 19, wherein said power supply connections are specified for connection to approximately 5 Volts of supply voltage, and said limiter has a threshold voltage of about 12 V. ### Claim 22 (depends on 19) The integrated circuit of claim 19, wherein said limiter has a dynamic on-resistance of no more than a few tens of ohms. ### Claim 23 (depends on 19) The integrated circuit of claim 19, wherein said limiter has a dynamic on-resistance of about 20 ohms. ### Claim 24 (depends on 19) The integrated circuit of claim 19, wherein said limiter comprises multiple Zener diodes in series.