# US 5,347,184 A · Dual receiver edge-triggered digital signal level detection system

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- Number: US 5,347,184 A
- Document ID: US5347184A
- Status: Granted
- Kind: A
- Application number: 07/998,166
- Filed: 1992-12-29
- Granted: 1994-09-13
- Earliest claimed: 1992-12-29
- Assignees: Texas Instruments Incorporated
- Inventors: Michael C. Stephens, Jr.; Roger D. Norwood; Duy-Loan T. Le; Kenneth A. Poteet
- Web page: https://patentgrep.com/patent/US5347184A

## CPC

- H03K 19/0963: {using transistors of complementary type (H03K19/0966 takes precedence)}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Two separate receivers (120,122) receive the input signal (128) and the clock signal (126). During the inactive state of the clock signal, the first receiver produces a low state output (130) and the second receiver produces a high state output (132). Both outputs feed combinational logic (124), which produces two outputs (142,144) both normally low. Upon transition of the clock signal, the output of only one of the receivers changes state to match the logic state of the input signal. The output of the other receiver maintains its logic state. Upon the change in the clock signal, only one of the combinational logic outputs changes state to a logical high state to indicate the state of the one input signal.

## Claims

### Claim 1

A level detection system receiving two input signals to indicate one or another logic state of the first input signal at the transition of the second input signal from an inactive state to an active state, the system comprising:
A. a first signal receiver having a first input receiving the first input signal, and a second input receiving the second input signal, the first signal receiver having an output producing an output signal of one logic state while the second input signal is inactive and an output signal of the same logic state as the first input signal While the second input signal is active;
B. a second signal receiver having a first input receiving the first input signal, and a second input receiving the second input signal, the second signal receiver having an output producing an output signal of another logic state while the second input signal is inactive and an output signal of the same logic state as the first input signal while the second input signal is active; and
C. combinational logic receiving the output signals from the two receivers and producing at least one indicate signal of the same logic state as the first input signal in response to a change in logic state in one of the outputs from the receivers.

### Claim 2 (depends on 1)

The system of claim 1 in which the combinational logic produces two indicate signals, a first indicating the first input signal being in one logic state at the transition of the second input signal, and a second indicating the first input signal being at the other logic state at the transition of the second input signal.

### Claim 3 (depends on 2)

The system of claim 2 in which the first input signal is column address strobe, CAS.sub.--, and the second input signal is row address strobe, RAS.sub.--, and the first indicate signal indicates a RAS.sub.-- before CAS.sub.-- condition and the second indicate signal indicates a CAS.sub.-- before RAS.sub.-- condition.

### Claim 4 (depends on 2)

The system of claim 2 in which the combinational logic includes a nand gate receiving the outputs of both receivers and producing the first indicate signal through an inverter, and the combinational logic includes a nor gate receiving the outputs of both receivers and producing the second indicate signal directly.

### Claim 5 (depends on 1)

The system of claim 1 in which the second input signal has an inactive high logic state and an active low logic state.

### Claim 6 (depends on 1)

The system of claim 1 in which the first signal receiver produces an output signal of a logic low state while the second input signal is inactive and the second signal receiver produces an output signal of a logic high state while the second input signal is inactive.

### Claim 7

A process of indicating one or another logic state of a first input signal at the transition of a second input signal from an inactive state to an active state, the process comprising:
A. producing an output signal of the one logic state while the second input signal is inactive and producing an output signal of the same logic state as the first input signal while the second input signal is active;
B. generating an output signal of the other logic state while the second input signal is inactive and generating an output signal of the same logic state as the first input signal while the second input signal is active; and
C. forming at least one indicate signal of the same logic state as the first input signal in response to a change in logic state in one of the produced and generated output signals.

### Claim 8 (depends on 7)

The process of claim 7 in which the first input signal is column address strobe, CAS.sub.--, the second input signal is row address strobe, RAS.sub.--, the RAS.sub.-- signal has an inactive high logic level state and an active low logic level state, and the one logic state is logic level low and the other state is logic level high, and, depending upon the state of CAS.sub.-- when RAS.sub.-- changes from inactive to active, the formed output signal indicates CAS.sub.-- before RAS.sub.-- and RAS.sub.-- before CAS.sub.--.