Inverting output driver circuit for reducing electron injection into the substrate

A space-efficient, inverting output driver circuit that reduces hot electron injection, said circuit comprising:

• first and second P-channel FETs;
• first, second, third, fourth and fifth N-channel FETs;
• each P-channel FET and each N-channel FET having, by definition, a gate, a source region, a drain region, and a channel region;
• said fifth N-channel FET having greater drive than said first P-channel FET;
• the gate of the first N-channel FET being coupled to a power supply voltage (V.sub.CC) through the second P-channel FET;
• the gates of the second P-channel FET, the fourth N-channel FET, and the fifth N-channel FET being permanently held at ground potential;
• an input node which is coupled to the gates of the first P-channel FET and the second N-channel FET;
• an intermediate node that is coupled to a power supply voltage (V.sub.CC) through the first P-channel FET, and to ground through both the first N-channel FET and the second N-channel FET, said first and second N-channel FETs being series coupled, with the first N-channel FET being electrically nearer the intermediate node;
• said intermediate node being coupled to the gate of the third N-channel FET;
• and
• a final output node that is coupled to V.sub.CC through the third N-channel FET, to the intermediate node through the fourth N-channel FET, and to the gate of the first N-channel FET through the fifth N-channel FET.

An output driver circuit comprising:

• an N-channel pull-up field effect transistor for coupling a final output node to a power supply voltage bus;
• an intermediate node coupled to the gate of said pull-up transistor;
• a tri-state inverter circuit which couples an input node to said intermediate node;
• means for clamping the intermediate node to the final output node whenever the intermediate node is in a low logic state, and the final output node drops more than a threshold voltage below ground potential.

A space-efficient, inverting output driver circuit that reduces hot electron injection, said circuit comprising:

• a first P-channel FET;
• first, second, third, fourth and fifth N-channel FETs;
• each P-channel FET and each N-channel FET having, by definition, a gate, a source region, a drain region, and a channel region;
• a resistive device;
• said fifth N-channel FET having greater drive than said resistive device;
• the gate of the second N-channel FET being coupled to a power supply voltage (V.sub.CC) through the resistive device;
• the gates of the fourth N-channel FET, and the fifth N-channel FET being permanently held at ground potential;
• an input node which is coupled to the gates of the first P-channel FET and the first N-channel FET;
• an intermediate node that is coupled to a power supply voltage (V.sub.CC) through the first P-channel FET, and to ground through both the first N-channel FET and the second N-channel FET, said first and second N-channel FETs being series coupled, with the first N-channel FET being electrically nearer the intermediate node;
• said intermediate node being coupled to the gate of the third N-channel FET;
• and
• a final output node that is coupled to V.sub.CC through the third N-channel FET, to the intermediate node through the fourth N-channel FET, and to the gate of the second N-channel FET through the fifth N-channel FET.

A space-efficient, inverting output driver circuit that reduces hot electron injection, said circuit comprising:

• a first P-channel FET;
• first, second, third, fourth and fifth N-channel FETs;
• each P-channel FET and each N-channel FET having, by definition, a gate, a source region, a drain region, and a channel region;
• a resistive device;
• said fifth N-channel FET having greater drive than said resistive device;
• the gate of the first N-channel FET being coupled to a power supply voltage (V.sub.CC) through the resistive device;
• the gates of the fourth N-channel FET, and the fifth N-channel FET being permanently held at ground potential;
• an input node which is coupled to the gates of the first P-channel FET and the second N-channel FET;
• an intermediate node that is coupled to a power supply voltage (V.sub.CC) through the first P-channel FET, and to ground through both the first N-channel FET and the second N-channel FET, said first and second N-channel FETs being series coupled, with the first N-channel FET being electrically nearer the intermediate node;
• said intermediate node being coupled to the gate of the third N-channel FET;
• and
• a final output node that is coupled to V.sub.CC through the third N-channel FET, to the intermediate node through the fourth N-channel FET, and to the gate of the first N-channel FET through the fifth N-channel FET.