# US 5,347,149 A · Integrated circuit and method

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- Number: US 5,347,149 A
- Document ID: US5347149A
- Status: Granted
- Kind: A
- Application number: 07/443,538
- Filed: 1989-11-29
- Granted: 1994-09-13
- Earliest claimed: 1989-11-29
- Assignees: Texas Instruments Incorporated
- Inventors: Burhan Bayraktaroglu
- Web page: https://patentgrep.com/patent/US5347149A

## CPC

- H10D 84/01: Manufacture or treatment
- H10D 84/05: using Group III-V technology
- H10D 86/01: Manufacture or treatment
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Integrated circuits and fabrication methods incorporating both two-terminal devices such as IMPATT diodes (446) and Schottky diodes (454) and three-terminal devices such as n-channel MESFETs (480) in a monolithic integrated circuit.

## Claims

### Claim 1

An integrated circuit including both two-terminal and three terminal devices, comprising:
(a) a first layer of semi-insulating semiconductor material including doped contact regions;
(b) a second layer of doped semiconductor material on said first, layer, said second layer including a plurality of electrically isolated regions, a first of said isolated regions forming an IMPATT diode avalanche drift region and located on one of said contact regions, and a second of said isolated regions forming a FET channel region and located straddling two of said contact regions;
(c) a top IMPATT region on said first disconnected region; and
(d) a gate over said FET channel region.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, further comprising:
(a) a third of said disconnected regions forming a Schottky diode semiconductor region; and
(b) a Schottky contact to said third isolated region.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein:
(a) said first layer is made of gallium arsenide; and
(b) said second layer is made of n-type gallium arsenide.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, further comprising:
(a) a ground plane on said first layer, said ground plane separated from said second layer by said first layer; and
(b) at least one conductive via extending from said ground plane through said first layer to one of said contact regions.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, further comprising:
(a) at least one transmission line formed by a conductive strip on said first layer and said ground plane, said transmission line coupled to one of said devices.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, further comprising:
(a) at least one air bridge connecting said top IMPATT region a conductor on said first layer.

### Claim 7 (depends on 2)

The integrated circuit of claim 2, further comprising:
(a) at least one air bridge connecting said top IMPATT region to a conductor on said first layer.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, further comprising:
(a) said top IMPATT region includes a second avalanche drift region.

### Claim 9

An integrated transmit/receive circuit, comprising:
(a) a power oscillator including a first diode, said power oscillator coupled to a first output;
(b) a first input;
(c) a variable oscillator including a second diode, said variable oscillator coupled to said first input;
(d) a mixer including a third diode, said mixer coupled to said variable oscillator and said first input; and
(e) an amplifier coupled to said mixer and to a second output;
(f) wherein said diodes are formed in corresponding disconnected regions of a semiconductor layer, said layer on a semi-insulating substrate.

### Claim 10 (depends on 9)

The integrated transmit/receive circuit of claim 9, wherein:
(a) said first diode is an IMPATT diode and said corresponding disconnected region is an avalanche drift region;
(b) said second diode is an IMPATT diode and said corresponding disconnected region is an avalanche drift region;
(c) said third diode is a Schottky diode and said corresponding disconnected region is a semiconductor portion of a Schottky barrier.

### Claim 11 (depends on 9)

The integrated transmit/receive circuit of claim 9, wherein:
(a) said amplifier includes at least one field effect transistor with a channel region formed in a corresponding disconnected region of said semiconductor layer.

### Claim 12 (depends on 9)

The integrated transmit/receive circuit of claim 9, wherein: (a) said variable oscillator includes a fourth diode, said fourth diode comprising a varactor and includes a corresponding disconnected region of said semiconductor layer.

### Claim 13 (depends on 9)

The integrated transmit/receive circuit of claim 9, wherein:
(a) said mixer is a balanced mixer and includes a fifth diode, said fifth diode is a Schottky diode and includes a corresponding disconnected region in said semiconductor layer and which is a semiconductor portion of a Schottky barier.