# US 5,346,862 A · Method for the electrical insulation of a circuit function element on a semiconductor component

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- Number: US 5,346,862 A
- Document ID: US5346862A
- Status: Granted
- Kind: A
- Application number: 08/055,351
- Filed: 1993-05-03
- Granted: 1994-09-13
- Earliest claimed: 1992-06-22
- Assignees: Siemens Aktiengesellschaft
- Inventors: Lothar Schleicher; Hans-Peter Zwicknagl; Elke Schoening
- Web page: https://patentgrep.com/patent/US5346862A

## CPC

- H10W 10/00: Isolation regions in semiconductor bodies between components of integrated devices
- H10W 10/01: {Manufacture or treatment}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Method for the electrical insulation of a function element on a semiconductor component, wherein the function element is etched into a mesa (9) using a mask (8). A dielectric (10) is then applied surface-wide at least up to the height of the mesa (9). The more deeply disposed portions of this dielectric layer are covered with photoresist (11), and the photoresist (11) is caused to flow by tempering and, thus, is caused to level the surface. Finally, the photoresist (11) and the dielectric (10) are re-etched with the same etching rate until the mesa is uncovered.

## Claims

### Claim 1

A method for the electrical insulation of a circuit function element on a semiconductor component, comprising the steps of:
etching the circuit function element to form a mesa;
applying a dielectric that completely covers the mesa surface-wide at least up to a height of the mesa;
employing a mask and applying photoresist having flowability with temperature treatment onto the portions of the dielectric present at the side of the mesa;
planarizing the surface of the dielectric with the flowing photoresist by heating; and
etching the photoresist and the dielectric with the same etching rate until the mesa is uncovered.

### Claim 2 (depends on 1)

A method according to claim 1, wherein said function element is a transistor.

### Claim 3 (depends on 2)

A method according to claim 2, wherein said step of etching the function element is further characterized by applying a mesa mask onto a top layer of the function element sized approximating the select top surface area of the mesa to be formed by the etching.

### Claim 4 (depends on 3)

A method according to claim 3, comprising the further step of after the step of etching the photoresist, removing the mesa mask.

### Claim 5 (depends on 2)

A method according to claim 2, wherein the dielectric is selected from the group consisting of Si.sub.3 N.sub.4, SiON or SiO.sub.2.

### Claim 6 (depends on 2)

A method according to claim 2, wherein the step of etching the photoresist is a dry etching step.

### Claim 7 (depends on 1)

A method according to claim 1, wherein the dielectric is selected from the group consisting of Si.sub.3 N.sub.4, SiON or SiO.sub.2.

### Claim 8 (depends on 7)

A method according to claim 7, wherein the step of etching the photoresist is a dry etching step.

### Claim 9 (depends on 1)

A method according to claim 1, wherein the step of etching the photoresist is a dry etching step.

### Claim 10 (depends on 1)

A method according to claim 1, wherein said step of etching the function element is further characterized by applying a mesa mask onto a top layer of the function element said mesa mask sized approximating the select top surface area of the mesa to be formed by the etching.

### Claim 11 (depends on 10)

A method according to claim 10, comprising the further step of after the step of etching the photoresist, removing the mesa mask.

### Claim 12 (depends on 1)

A method according to claim 1, wherein said step of employing a mask is further characterized in that the photoresist is applied to a level approximately equal to the height of the dielectric above the mesa and not covering the dielectric above the mesa.