# US 5,346,848 A · Method of bonding silicon and III-V semiconductor materials

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- Number: US 5,346,848 A
- Document ID: US5346848A
- Status: Granted
- Kind: A
- Application number: 08/070,068
- Filed: 1993-06-01
- Granted: 1994-09-13
- Earliest claimed: 1993-06-01
- Assignees: Motorola, Inc.
- Inventors: Melissa E. Grupen-Shemansky; Bertrand F. Cambou
- Web page: https://patentgrep.com/patent/US5346848A

## CPC

- H10P 90/1914: {using bonding}
- Y10S 148/012: Bonding, e.g. electrostatic for strain gauges
- Y10S 148/135: Removal of substrate
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A silicon wafer and a III-V semiconductor wafer are bonded together through a bonding interlayer which is deposited on the III-V semiconductor wafer. By forming the bonding interlayer on the III-V semiconductor wafer, rather than the silicon wafer, the bonding process is facilitated, creating a sufficiently strong bond to carry out further processing. The III-V semiconductor wafer is thinned to relieve stress after the bonding procedure. The bonded wafers may be subjected to a second bonding procedure to increase the bond strength. The bonded wafers can then be subjected to high temperature processing used in semiconductor device fabrication.

## Claims

### Claim 1

A method of bonding a silicon wafer and a III-V semiconductor wafer, comprising the steps of:
providing a silicon wafer having a first and a second major surface;
providing a III-V semiconductor wafer having a first and a second major surface;
forming a bonding interlayer on the first major surface of the III-V semiconductor wafer;
bonding the silicon wafer and the III-V semiconductor wafer together by using a first thermal or a thermo-anodic bonding process, such that the bonding interlayer is positioned between the III-V semiconductor wafer and the first major surface of the silicon wafer;
removing a portion of the III-V semiconductor wafer from the second major surface of the III-V semiconductor wafer; and subjecting the III-V semiconductor wafer and the silicon wafer to a second thermal or thermo-anodic bonding process at a temperature less than approximately 200.degree. C. after the step of removing a portion of the III-V semiconductor wafer.

### Claim 2 (depends on 1)

The method of claim 1 further comprising removing a portion of the silicon wafer from the second major surface after the step of bonding.

### Claim 3 (depends on 1)

The method of claim 1 wherein the step of bonding further comprises bonding at a temperature less than approximately 200.degree. C.

### Claim 4 (depends on 1)

The method of claim 1 further comprising the steps of:
forming a plurality of trenches, each having a bottom, in the first major surface of the III-V semiconductor wafer before the step of forming the bonding interlayer such that the bonding interlayer is also formed in each of the plurality of trenches; forming a planarizable layer on the bonding interlayer on first major surface of the III-V semiconductor wafer and in the trenches; and wherein the step of removing a portion of the III-V semiconductor wafer further comprises removing a portion of the III-V semiconductor wafer down to at least the bottom of each of the plurality of trenches.

### Claim 5 (depends on 1)

The method of claim 1 further comprising the steps of:
forming a plurality of trenches, each having a bottom, in the first major surface of the III-V semiconductor wafer before the step of forming the bonding interlayer such that the bonding interlayer is also formed in each of the plurality of trenches; and wherein the step of removing a portion of the III-V semiconductor wafer further comprises removing a portion of the III-V semiconductor wafer to form a plurality of regions comprised of the III-V semiconductor wafer and the bonding interlayer, wherein the plurality of the regions have sidewalls.

### Claim 6 (depends on 5)

The method of claim 5 further comprising altering the sidewalls of the plurality of regions so that the sidewalls are sloped at approximately a 45 degree angle.

### Claim 7 (depends on 1)

The method of claim 1 wherein the step of forming the bonding interlayer comprises forming a layer or combination of layers selected from the list of silicon dioxide, doped silicon dioxide, silicon nitride, polysilicon, or amorphous silicon.

### Claim 8 (depends on 1)

The method of claim 1 wherein the step of forming the bonding interlayer consists essentially of forming a layer or combination of layers selected from the list of silicon dioxide, doped silicon dioxide, silicon nitride, polysilicon, or amorphous silicon.

### Claim 9 (depends on 1)

The method of claim 1 wherein the step of forming the bonding interlayer consists essentially of forming a silicon nitride layer on the III-V semiconductor wafer and a silicon dioxide layer on the silicon nitride layer.