# US 5,346,843 A · Method of manufacturing a semiconductor device having a memory cell and peripheral circuit including forming a first electrode for the capacitor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 5,346,843 A
- Document ID: US5346843A
- Status: Granted
- Kind: A
- Application number: 07/871,705
- Filed: 1992-04-21
- Granted: 1994-09-13
- Earliest claimed: 1991-04-30
- Assignees: Sony Corporation
- Inventors: Hideaki Kuroda
- Web page: https://patentgrep.com/patent/US5346843A

## CPC

- H10B 12/31: {having a storage electrode stacked over the transistor}
- Y10S 438/97: Specified etch stop material
- H10B: ELECTRONIC MEMORY DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

According to this invention, a conductive film for forming a plate electrode of a capacitor constituting a memory cell is patterned in only a memory cell region at first. After the conductive film in a peripheral circuit region is used as a stopper for wet-etching a low-melting insulating film of the peripheral circuit region, the conductive film is patterned using the same mask as the low-melting insulating film or the low-melting insulating film itself as a mask. For this reason, an SiN film formed by a low pressure CVD method is not used as a stopper, and an additional lithographic step is not required. Therefore, while a memory cell region is planarized and the step of the peripheral circuit region is reduced, data retaining characteristics can be improved without increasing the number of steps.

## Claims

### Claim 1

A method of manufacturing a semiconductor memory having a memory cell region and a peripheral circuit region, and a memory cell being constituted by a transistor and a capacitor, comprising the steps of:
forming a conductive film which comprises a first electrode for a plate electrode of said capacitor;
forming a first resist on an entire surface of said peripheral circuit and memory cell regions;
patterning said conductive film using said first resist as a mask to form said first electrode;
forming a first insulating film on said conductive film so as to planarize said conductive film;
forming a second resist on the entire surface of said memory cell region;
removing said first insulating film from said peripheral circuit region by wet etching using said second resist as a mask;
removing said conductive film from said peripheral circuit region using said second resist as a mask; and
removing said second resist.

### Claim 2

A method of manufacturing a semiconductor memory having a memory cell region and a peripheral circuit region, and a memory cell being constituted by a transistor and a capacitor, comprising the steps of:
forming a conductive film which comprises a first electrode for a plate electrode of said capacitor;
forming a first resist on the surface of said peripheral circuit and memory cell regions;
patterning said conductive film using said first resist as a mask to form said first electrode;
forming a first insulating film on said conductive film so as to planarize said conductive film;
forming a second resist on the surface of at least said memory cell region;
removing said first insulating film from said peripheral circuit region by wet etching using said second resist as a mask;
removing said second resist; and
removing said conductive film from said peripheral circuit region using said first insulating film as a mask.

### Claim 3 (depends on 1, 2)

A method according to claim 1 or claim 2 wherein during the step of removing said first insulating film said conductive film is used as a stopper.

### Claim 4 (depends on 1)

A method according to claim 1 including depositing a BPSG film on said first electrode.

### Claim 5 (depends on 2)

A method according to claim 2 including depositing a BPSG film on said first electrode.