# US 5,346,833 A · Simplified method of making active matrix liquid crystal display

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- Number: US 5,346,833 A
- Document ID: US5346833A
- Status: Granted
- Kind: A
- Application number: 08/043,669
- Filed: 1993-04-05
- Granted: 1994-09-13
- Earliest claimed: 1993-04-05
- Assignees: Industrial Technology Research Institute
- Inventors: Biing-Seng Wu
- Web page: https://patentgrep.com/patent/US5346833A

## CPC

- H10D 86/0231: {using masks, e.g. half-tone masks}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6743: {Silicon}
- H10D 86/40: characterised by multiple TFTs
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

An inverted staggered (bottom gate) thin film transistor (TFT) for active matrix liquid crystal display is processed with three masks. The first mask is used to pattern a metal film on a glass substrate as the gate of the TFT, the scan line of the TFT array, and a portion of the data line of the TFT array. The second mask is used to form a TFT mesa with a gate dielectric layer, an a-Si layer as channel, and a heavily-doped n+s-Si layer for contacting the source and the drain of the TFT. A third mask is used to pattern the transparent conductive indium-tin oxide film as the pixel electrode, the source/drain electrodes of the TFT, and the interconnections of the data line.

## Claims

### Claim 1

A three mask method of fabricating an inverted staggered thin film transistor of an inverted staggered structure for active matrix crystal display systems with a matrix of picture elements, each thin film transistor having a gate, a source, and a drain, comprising the steps of:
depositing a metal film on a transparent substrate;
patterning said metal film as said gate electrode of said thin film transistor, as scan lines, and as data lines using a first mask;
successively depositing an insulating layer, an amorphous semiconductor layer, and a heavily doped amorphous semiconductor layer over said transparent substrate;
simultaneously patterning said insulating layer, said amorphous semiconductor layer, and said heavily doped amorphous semiconductor layer using a second mask to form a mesa;
depositing a transparent conducting layer over said mesa; and
patterning said transparent conducting layer using a third mask to form electrodes of picture elements, and crossover connections of said data lines at cross-points with said scan lines.

### Claim 2 (depends on 1)

A three-mask method of making a thin film transistor as described in claim 1, wherein said substrate is glass.

### Claim 3 (depends on 1)

A three-mask method of making a thin film transistor as described in claim 1, wherein said metal is selected from a group consisting of chromium and aluminum.

### Claim 4 (depends on 1)

A three-mask method of making a thin film transistor as described in claim 1, wherein said insulating layer is silicon-nitride.

### Claim 5 (depends on 1)

A three-mask method of making a thin film transistor as described in claim 1, wherein said amorphous semiconductor is amorphous silicon.

### Claim 6 (depends on 1)

A three-mask method of making a thin film transistor as described in claim 1, wherein said heavily doped semiconductor is heavily doped silicon.

### Claim 7 (depends on 1)

A three-mask method of making a thin film transistor as described in claim 1, wherein said transparent conductive layer is tin-indium-oxide.