# US 5,346,587 A · Planarization of a gate electrode for improved gate patterning over non-planar active area isolation

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- Number: US 5,346,587 A
- Document ID: US5346587A
- Status: Granted
- Kind: A
- Application number: 08/105,276
- Filed: 1993-08-12
- Granted: 1994-09-13
- Earliest claimed: 1993-08-12
- Assignees: Micron Semiconductor, Inc.
- Inventors: Trung T. Doan; Charles H. Dennison
- Web page: https://patentgrep.com/patent/US5346587A

## CPC

- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention is a process for providing a planarized transistor gate on a non-planar starting substrate, by depositing a layer of planarized conductive polysilicon material overlying neighboring field oxide isolation regions such that the height of the conductive polysilicon material extends above the topology of the field oxide isolation regions; depositing a layer of conductive silicide material superjacent and coextensive the conductive polysilicon material; and then patterning the planarized conductive polysilicon material and the conductive silicide material thereby forming the planarized transistor gate.

## Claims

### Claim 1

A process for providing a planarized conductor on a non-planar starting substrate, said process comprising the steps of:
forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said conductive material extends above the topology of said isolation regions;
forming a layer of reflective material superjacent and coextensive said planarized conductive material; and
patterning said conductive material thereby forming said planarized conductor.

### Claim 2 (depends on 1)

The process of claim 1, wherein said reflective material comprises a layer of reflective conductive material.

### Claim 3 (depends on 1)

The process of claim 1, wherein said reflective material comprises a layer of partially reflective insulative material.

### Claim 4 (depends on 1)

The process of claim 1, wherein said layer of planarized conductive material is planarized by chemical mechanical polishing.

### Claim 5 (depends on 1)

The process of claim 1, wherein said layer of planarized conductive material comprises conductively doped polysilicon.

### Claim 6 (depends on 2)

The process of claim 2, wherein said layer of reflective conductive material comprises a material selected from the group of metal silicides and metals.

### Claim 7 (depends on 6)

The process of claim 6, wherein said metal silicides comprise the group of tungsten silicide and titanium silicide.

### Claim 8 (depends on 3)

The process of claim 3, wherein said partially reflective insulating material comprises nitride.

### Claim 9

A process for providing a planarized transistor gate on a non-planar starting substrate, said process comprising the steps of:
forming a layer of planarized conductive material overlying neighboring isolation regions such that the height of said conductive material extends above the topology of said isolation regions;
forming a layer of reflective material superjacent and coextensive said planarized conductive material; and
patterning said conductive material thereby forming said thereby forming said planarized transistor gate.

### Claim 10 (depends on 9)

The process of claim 9, wherein said layer of reflective material comprises reflective conductive material.

### Claim 11 (depends on 9)

The process of claim 9, wherein said reflective material comprises a layer of partially reflective insulative material.

### Claim 12 (depends on 9)

The process of claim 9, wherein said layer of planarized conductive material is planarized by chemical mechanical polishing.

### Claim 13 (depends on 9)

The process of claim 9, wherein said layer of planarized conductive material comprises conductively doped polysilicon.

### Claim 14 (depends on 10)

The process of claim 10, wherein said layer of reflective conductive material comprises a material selected from the group of metal silicides and metals.

### Claim 15 (depends on 14)

The process of claim 14, wherein said metal silicides comprise the group of tungsten silicide and titanium silicide.

### Claim 16 (depends on 11)

The process of claim 11, wherein said partially reflective insulating material comprises nitride.

### Claim 17 (depends on 9)

The process of claim 9, wherein said layer of planarized conductive material comprises in-situ conductively doped polysilicon.

### Claim 18 (depends on 9)

The process of claim 9, wherein said layer of planarized conductive polysilicon material is approximately 3000.ANG. thick.

### Claim 19 (depends on 9)

The process of claim 9, wherein said layer of planarized conductive polysilicon material has a thickness of approximately 1000.ANG. overlying said field oxide.