# US 5,346,117 A · Method of fabricating a parallel processor package

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- Number: US 5,346,117 A
- Document ID: US5346117A
- Status: Granted
- Kind: A
- Application number: 08/097,604
- Filed: 1993-07-27
- Granted: 1994-09-13
- Earliest claimed: 1993-07-27
- Assignees: International Business Machines Corporation
- Inventors: Harold Kohn; Donald J. Lazzarini
- Web page: https://patentgrep.com/patent/US5346117A

## CPC

- H05K 3/4635: {laminating flexible circuit boards using additional insulating adhesive materials between the boards}
- G06F 13/409: {Mechanical coupling (back panels H05K7/1438)}
- H05K 3/462: {characterized by laminating only or mainly similar double-sided circuit boards}
- H05K 1/0393: {Flexible materials (H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups)}
- H05K 3/328: by welding
- H05K 3/4038: {Through-connections; Vertical interconnect access [VIA] connections (H05K3/403, H05K3/42 take precedence)}
- H05K 3/4623: {the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards (H05K3/462 takes precedence)}
- H05K 3/4626: {characterised by the insulating layers or materials (H05K3/4688 takes precedence)}
- H05K 3/4641: {having integrally laminated metal sheets or special power cores}
- H05K 2201/0305: Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
- H05K 2201/0373: Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
- H05K 2201/09536: Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
- H05K 2201/09572: Solder filled plated through-hole in the final product
- H05K 2201/096: Vertically aligned vias, holes or stacked vias
- H05K 2201/10159: Memory
- Y10T 29/49126: Assembling bases
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

Disclosed is a method for manufacturing a stacked circuitized flex structure. The structure is a laminate for Z-axis communication within a parallel processor. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Z-axis circuitization is carried out by providing vias and through holes in individual circuitized flex strips. These vias and through holes are circuited and plated. This is followed by filling the vias and through holes with solder and forming solder bumps at the tops and bottoms of the vias and through holes. A sticker sheet with clearance holes for the solder bumps is provided, and a plurality of the circuitized flex strips are laid up for lamination to form a stack of circuitized flexible strips. Lamination is carried out at elevated pressure and temperature to crush the solder bumps, bond, and homogenize solder bump material and fuse the sticker sheets. Next, the stack is cooled to solidify the homogenized solder bump material.

## Claims

### Claim 1

A method of fabricating a parallel processor structure having a plurality of processor integrated circuit chips, and a plurality of memory integrated circuit chips, with signal interconnection circuitization means therebetween, wherein
a. the processor integrated circuit chips and the memory integrated circuited chips are mounted on a plurality of printed circuit cards and boards with a first processor integrated circuit printed circuit board having a first processor integrated circuit chip mounted thereon, a second processor integrated circuit printed circuit board having a second processor integrated circuit chip mounted thereon, a first memory integrated circuit printed circuit board having a first memory integrated circuit chip mounted thereon, and a second memory integrated circuit printed circuit board having a second memory integrated circuit chip mounted thereon;
b. said printed circuit cards and boards are mounted on a plurality of circuitized flexible strips, said circuitized flexible strips having a signal interconnection circuitization portion with X-Y planar circuitization and vias and through holes for Z-axis circuitization, a terminal portion having means for joining a printed circuit board thereto, and a flexible, circuitized portion between said signal interconnection circuitization portion and said terminal portion, and
c. said circuitized flexible strips being joined at a signal interconnection circuitization body portion having X-axis, Y-axis, and Z-axis signal interconnection between processor integrated circuit chips and memory integrated circuit chips and comprising a laminate of said circuitized flexible strips at their signal interconnection circuitization portions, whereby said circuitized flexible strips are laminated in physical and electrical connection at their signal interconnection circuitization portions and spaced apart at their terminal portions;
said process comprising selectively forming electrical interconnections between separate circuitized flexible strips by:
a. providing vias and through holes in individual circuitized flex strips;
b. circuitizing and plating the vias and through holes;
c. filling the vias and through holes with solder and forming solder bumps at the tops and bottoms of the vias and through holes;
d. providing a sticker sheet with clearance holes for the solder bumps;
e. laying up a plurality of the circuitized flexible strips to form a stack of circuitized flexible strips;
f. applying an elevated pressure and temperature to the stack to crush the solder bumps, bond, and homogenize solder bump material and fuse the sticker sheets; and
g. cooling the stack to solidify the homogenized solder bump material.

### Claim 2 (depends on 1)

The method of claim 1 wherein the solder bumps are thicker than the sticker sheet to allow the solder bumps to extend beyond the sticker sheet.

### Claim 3 (depends on 1)

The method of claim 1 wherein the sticker sheet comprises a B-stage epoxy resin.

### Claim 4 (depends on 1)

The method of claim 1 comprising applying a pressure of at least about 100 psi to the stack to crush the solder bumps.

### Claim 5 (depends on 1)

The method of claim 1 comprising heating the stack to at least about 300 degrees F. to fuse the sticker sheets to the circuitized flex surfaces.

### Claim 6 (depends on 5)

The method of claim 5 comprising thereafter heating the stack to at least about 380 degrees Fahrenheit to bond and homogenize the solder bumps.