# US 5,345,564 A · Serial communication peripheral integrated electronic circuit that recognizes its unique address before the entire circuit is enabled

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- Number: US 5,345,564 A
- Document ID: US5345564A
- Status: Granted
- Kind: A
- Application number: 07/861,298
- Filed: 1992-03-31
- Granted: 1994-09-06
- Earliest claimed: 1992-03-31
- Assignees: Zilog, Inc.
- Inventors: Bradley D. Jensen; Ed Morson
- Web page: https://patentgrep.com/patent/US5345564A

## CPC

- G06F 1/3237: by disabling clock generation or distribution
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/325: {Power saving in peripheral device}
- G06F 13/423: {with synchronous protocol}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A peripheral integrated electronic circuit of the type having an interface for serially transferring data between it and a central processing unit ("CPU") in a computer system that employs a number of such peripheral circuits that are selectively rendered operable by the CPU, one at a time. The peripherals each include an interface that receives an initial data word from the CPU that identifies the peripheral circuit with which data is to be transferred by the CPU. Rather than all such peripherals in a computer system being powered-up in order to have their processors determine individually under software control whether they have been identified by the CPU, only a small hardwired interface circuit is so enabled. Once this interface circuit determines that the CPU desires to conduct data transfer with it, the main portion of the circuit, including its processor, is then powered-up.

## Claims

### Claim 1

In a computer system having a central processing unit ("CPU") connected in parallel with at least two peripheral units that contain unique identification codes and have internal processors, a method of activating a selected one of said at least two peripheral units to operate with the CPU, comprising the steps of:
causing the CPU to transmit one of the unique identification codes to all of said at least two peripheral units,
comparing in a hardware circuit of each of said at least two peripheral units its unique identification code with the identification code being transmitted by the CPU, said comparing step occurring without activating the internal processors in any of said at least two peripheral units,
selecting one of said at least two processing units wherein its unique identification code matches the transmitted identification code, and
activating the internal processor within the selected one of said at least two processing units by supplying a clock signal to the internal processor of the selected peripheral processing unit without activating the internal processor in any other of said at least two peripheral units.

### Claim 2 (depends on 1)

The method according to claim 1 wherein the comparing step includes activating an interface portion of each of said at least two peripheral units by starting a clock signal thereto without providing a clock signal to their internal processors.

### Claim 3

A peripheral integrated electronic circuit adapted to be connected along with other such circuits to a central computer system processor, comprising:
an internal processor,
a clock source,
means connectable to serially receive data from the central processor for temporarily storing said data,
programmable means for storing an identification code of the peripheral circuit, and
comparator means connected to said data receiving means and to said programmable means for connecting said clock source to the internal processor in response to a correspondence between data in said data receiving means and an identification code stored in said identification code storing means, thereby to render the internal processor operable when the peripheral circuit receives its identification code as data from the central computer system processor.