# US 5,345,420 A · Semiconductor memory device

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- Number: US 5,345,420 A
- Document ID: US5345420A
- Status: Granted
- Kind: A
- Application number: 08/067,318
- Filed: 1993-05-25
- Granted: 1994-09-06
- Earliest claimed: 1986-10-27
- Assignees: Seiko Epson Corporation
- Inventors: Hirofumi Yasuda; Akira Uematsu
- Web page: https://patentgrep.com/patent/US5345420A

## CPC

- G11C 17/12: using field-effect devices
- G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs}
- G11C 7/18: Bit line organisation; Bit line lay-out
- H10B 20/00: Read-only memory [ROM] devices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device for reading data from a selected memory cell. The memory cells are arranged in an array. First bit lines and word lines, coupled to the memory cells, are arranged in a matrix. The word lines select the selected cell. An amplification circuit amplifies the current passing through the selected memory cell and is coupled to the first bit line. A second bit line is coupled to the amplification circuit and carries the amplified current. A sensing circuit coupled to the second bit line senses the current on the second bit line. As a result, the current passing through the selected memory cell is detected.

## Claims

### Claim 1

A semiconductor memory device for reading data from a selected memory cell where the memory cells are arranged in an array and first bit lines and word lines coupled to the memory cells are arranged in a matrix, the word lines selecting the selected cell, the semiconductor memory device comprising:
a first bit line coupled to a group of memory cells for carrying the current passing through the selected memory cell;
first amplification means coupled to the first bit line for amplifying the current on the first bit line;
a second bit line coupled to the first bit line through the first amplification means for carrying the amplified current;
second amplification means coupled to the second bit line for further amplifying the current on the second bit line;
a third bit line coupled to the second bit line through the second amplification means for carrying the further amplified current; and
sensing means coupled to the third bit line for sensing the current on the third bit line, whereby the current passing through the selected memory cell is detected.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1 wherein there are at least two third bit lines and further comprising selection means for selectively coupling one of the third bit lines to the sensing means.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1 wherein there are at least two second bit lines coupled through separate second amplification means to the third bit line.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1 wherein at least two first bit lines are coupled to the second bit lines through separate first amplification means.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1 wherein each memory cell is formed of a MOS transistor.

### Claim 6 (depends on 5)

The semiconductor memory device of claim 5 wherein the first bit line is coupled to one of the source and drain electrodes of the MOS transistors forming the memory cells.

### Claim 7 (depends on 1)

The semiconductor memory device of claim 1 wherein a plurality of the memory cells are coupled to the first amplification means in parallel.

### Claim 8 (depends on 1)

The semiconductor memory device of claim 1 wherein a plurality of the memory cells are coupled to the first amplification means in series.

### Claim 9 (depends on 1)

The semiconductor memory device of claim 1 wherein the first bit line and the second bit line are formed as separate layers, separated by an insulating layer.