# US 5,345,357 A · ESD protection of output buffers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,345,357 A - Document ID: US5345357A - Status: Granted - Kind: A - Application number: 07/894,405 - Filed: 1992-06-05 - Granted: 1994-09-06 - Earliest claimed: 1992-06-05 - Assignees: AT&T Bell Laboratories - Inventors: Juergen Pianka - Web page: https://patentgrep.com/patent/US5345357A ## CPC - H10D 89/811: {using FETs as protective elements} - H10D 89/601: {for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A particular electrostatic discharge (ESD) protection problem is faced when only n-channel output transistors are present, since there is no p-n junction that could serve to clamp positive ESD voltages, as would be the case if a p-channel output transistor were present. In the present technique, a capacitor couples a bond pad to the gate of a protective transistor that applies a turn-on voltage to the gate of an n-channel output transistor. In this manner, the output transistor itself is used to conduct the ESD current to a power supply conductor (V.sub.SS). In one embodiment, to assist in the turn-on of the n-channel output transistor, a transistor couples the bond pad to the n-tub in which the p-channel pre-driver transistor is formed. Conduction through this transistor raises the n-tub voltage when an ESD event occurs, thereby preventing the p-n junction of the p-channel driver transistor from clamping the turn-on voltage, which would limit the protection obtained by this technique. This technique is especially valuable for SCSI (Small Computer System Interface) chips, since only n-channel output transistors are used. It may also be used in TTL-output buffers, which also use n-channel pull-up and pull-down devices. P-channel output devices may be comparably protected. ## Claims ### Claim 1 An integrated circuit comprising an output transistor having: a first controlled electrode coupled to a power supply conductor, a second controlled electrode coupled to an output conductor, and a control electrode coupled to receive an information signal; characterized in that said integrated circuit further comprises a protective device having: a first controlled electrode coupled to said output conductor, a second controlled electrode coupled to the control electrode of said output transistor, and a control electrode coupled to said output conductor so as to cause said output transistor to conduct during an electrostatic discharge; wherein said protective device is a field effect transistor, and further comprising a capacitor connected between said output conductor and the gate of said protective transistor; and still further comprising a resistor connected between the gate of said protective transistor and a power supply conductor, so that said protective transistor does not conduct in the absence of an electrostatic discharge event. ### Claim 2 (depends on 1) The integrated circuit of claim 1 wherein said output transistor is an n-channel field effect transistor, and said information signal is supplied by a pre-driver stage that includes a p-channel pull-up transistor that is located in an n-type tub region; and wherein said integrated circuit further comprises means for increasing the voltage on said n-type tub region during an electrostatic discharge event. ### Claim 3 (depends on 2) The integrated circuit of claim 2 wherein said means for increasing the voltage on said n-type tub region comprises a transistor having a first source/drain region connected to said output conductor, and a second source/drain region connected to said tub. ### Claim 4 (depends on 2) The integrated circuit of claim 2 wherein said means for increasing the voltage on said n-type tub region comprises a resistor connected between said n-type tub and the positive power supply voltage conductor. ### Claim 5 (depends on 2) The integrated circuit of claim 2 wherein said protective device provides for said output transistor to conduct when the electrostatic discharge event produces a voltage on said output conductor that rises more rapidly than 100 volts per nanosecond. ### Claim 6 An integrated circuit comprising an output transistor having a first source/drain region of a given conductivity type coupled to a power supply conductor and a second source/drain region of said given conductivity type coupled to an output conductor, and a gate coupled to a pre-driver circuit, characterized in that said integrated circuit further comprises: a protective transistor having a first source/drain region of said given conductivity type coupled to the gate of said output transistor, a second source/drain region of said given conductivity type coupled to said output conductor, and a gate coupled to said output conductor through a capacitor; and still further comprises a resistor coupled between the gate of said protective transistor and a power supply conductor so that said protective transistor does not conduct in the absence of an electrostatic discharge event. ### Claim 7 (depends on 6) The integrated circuit of claim 6 wherein said output transistor is an n-channel field effect transistor, and said pre-driver circuit includes a p-channel pull-up transistor that is located in an n-type region; and wherein said integrated circuit further comprises means for increasing the voltage on said n-type tub region during an electrostatic discharge event. ### Claim 8 (depends on 7) The integrated circuit of claim 7 wherein said means for increasing the voltage on said n-type tub region comprises a transistor having a first source/drain region connected to said output conductor, and a second source/drain region connected to said tub, and a gate connected to the gate of said protective transistor. ### Claim 9 (depends on 7) The integrated circuit of claim 7 wherein said means for increasing the voltage on said n-type tub region comprises a resistor connected between said n-type tub and the positive power supply voltage conductor. ### Claim 10 (depends on 6) The integrated circuit of claim 6 wherein said given conductivity type is n-type. ### Claim 11 (depends on 6) The integrated circuit of claim 6 wherein said protective transistor provides for said output transistor to conductor when the electrostatic discharge event produces a voltage on said output conductor that rises more rapidly than 100 volts per nanosecond. ### Claim 12 An integrated circuit comprising: a field effect pull-up transistor of a given conductivity type having a source coupled to a positive power supply conductor, a drain coupled to an output conductor, and a gate coupled to receive an information signal; and a field effect pull-down transistor of said given conductivity type having a source coupled to a negative power supply conductor, a drain coupled to said output conductor, and a gate coupled to receive said information signal; characterized in that said integrated circuit further comprises first and second field effect protective transistors, both of said given conductivity type; wherein the first protective transistor has a first source/drain electrode coupled to the gate of said pull-up transistor, a second source/drain electrode coupled to said output conductor, and a gate electrode; and wherein the second protective transistor has a first source/drain electrode coupled to the gate of said pull-down transistor, a second source/drain electrode coupled to said output conductor, and a gate electrode; and still further comprises means for coupling the gate electrodes of said first and second protective transistors to said output conductor so as to cause said pull-up and pull-down transistors to conduct during an electrostatic discharge event. ### Claim 13 (depends on 12) The integrated circuit of claim 12 wherein said means for coupling the gate electrodes of said protective transistors to said output conductor comprises a capacitor connected between said gate electrodes and said output conductor; and wherein said integrated circuit further comprises a resistor connected from the gate electrodes of said protective transistors to a power supply conductor so that said protective transistors do not conduct in the absence of an electrostatic discharge event. ### Claim 14 (depends on 12) The integrated circuit of claim 12 wherein said given conductivity type is n-type. ### Claim 15 (depends on 14) The integrated circuit of claim 14 wherein said information signal is supplied by a pre-driver stage that includes a p-channel pull-up transistor that is located in an n-type tub region; and wherein said integrated circuit further comprises means for increasing the voltage on said n-type tub region during an electrostatic discharge event. ### Claim 16 (depends on 15) The integrated circuit of claim 15 wherein said means for increasing the voltage on said n-type tub region comprises a transistor having a first n-type source/drain region connected to said output conductor, and a second n-type source/drain region connected to said tub region. ### Claim 17 (depends on 16) The integrated circuit of claim 16 wherein said means for increasing the voltage on said n-type region comprising a resistor connected between said n-type tub region and the positive power supply voltage conductor.