# US 5,345,195 A · Low power V.sub.cc and temperature independent oscillator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,345,195 A - Document ID: US5345195A - Status: Granted - Kind: A - Application number: 07/964,761 - Filed: 1992-10-22 - Granted: 1994-09-06 - Earliest claimed: 1992-10-22 - Assignees: United Memories, Inc.; Nippon Steel Semiconductor Corporation - Inventors: Michael V. Cordoba; Kim C. Hardee - Web page: https://patentgrep.com/patent/US5345195A ## CPC - H03K 3/0315: {Ring oscillators} - H03K 3/011: Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method :for refreshing a DRAM are also disclosed. ## Claims ### Claim 1 A low power oscillator circuit comprising: a first delay circuit including a constant current source which is substantially independent of variations in a supply voltage Vcc and temperature and a charge storage device coupled to the constant current source to establish a period of oscillator determined by the current generated in the constant current source; a latch coupled to the first delay circuit to provide a stable output; a second delay circuit coupled to receive the output from said latch and provide an oscillating output pulse signal; and an electrical connection from the second delay circuit to said first delay circuit. ### Claim 2 (depends on 1) The low power oscillator circuit of claim 1 further including a current limiting circuit coupled to said charge storage device to limit current loss and power dissipation. ### Claim 3 (depends on 1) The low power oscillator circuit of claim 1 wherein said oscillating output pulse frequency is inversely proportional to V.sub.CC. ### Claim 4 (depends on 1) The low power oscillator circuit of claim 1 wherein said oscillating output pulse signal is used to refresh a DRAM. ### Claim 5 (depends on 1) The low power oscillator circuit of claim 1 wherein the charge storage device is a capacitor. ### Claim 6 (depends on 1) The low power oscillator circuit of claim 1 wherein the second delay circuit includes a series of inverters. ### Claim 7 The low power oscillator circuit for refreshing a DRAM comprising: a constant current source which is substantially independent of variations in a supply voltage Vcc and temperature, wherein the constant current source includes first and second p-channel transistors coupled between a first voltage connection and a second voltage connection; wherein the gate electrode of the first transistor is coupled to the source of the second transistor and the gate electrode of the second transistor is coupled to the drain of the first transistor; first and second resistors, wherein said first resistor is coupled between the drain of the first transistor and the first voltage connection and the second resistor is coupled between the source of the second transistor and the second voltage connection; and wherein the source of the first transistor is coupled to the second voltage connection and the drain of the second transistor outputs a constant current; a capacitor coupled to the constant current source to substantially establish the period of oscillation determined by the current generated in the constant current source; said constant current source and said capacitor forming a first delay circuit; a current limiting circuit coupled to said capacitor to limit current loss and power dissipation; a latch coupled to said current limiting circuit to provide a stable output; a second delay circuit including a series of inverters coupled to receive the output from said latch and provide an oscillating output pulse signal which is inversely proportional to V.sub.CC ; and an electrical connection from the second delay circuit to said first delay circuit. ### Claim 8 A low power oscillator circuit comprising: a first delay circuit including a constant current source which is substantially independent of variations in a supply voltage Vcc and temperature and a charge storage device coupled to the constant current source to establish a period of oscillation determined by a current generated in the constant current source; a differential amplifier coupled to the charge storage device to provide an output when the charge storage device is charged to a certain voltage by the constant current source; a latch coupled to the output of the differential amplifier to provide a stable output; a second delay circuit coupled to receive the output from said latch and provide an oscillating output pulse signal; and an electrical connection from the second delay circuit to said first delay circuit. ### Claim 9 (depends on 8) The low power oscillator circuit of claim 8 further including a current limiting circuit coupled to said differential amplifier to limit current loss and power dissipation. ### Claim 10 (depends on 8) The low power oscillator circuit of claim 8 wherein said oscillating output pulse signal is used to refresh a DRAM. ### Claim 11 (depends on 8) The low power oscillator circuit of claim 8 wherein said constant current source includes first and second p-channel transistors coupled between a first voltage connection and a second voltage connection; wherein the gate electrode of the first transistor is coupled to the source of the second transistor and the gate electrode of the second transistor is coupled to the drain of the first transistor; first and second resistors, wherein said first resistor is coupled between the drain of the first transistor and the first voltage connection and the second resistor is coupled between the source of the second transistor and the second voltage connection; and wherein the source of the first transistor is coupled to the second voltage connection and the drain of the second transistor outputs a constant current. ### Claim 12 (depends on 8) The low power oscillator circuit of claim 8 wherein the charge storage device is a capacitor. ### Claim 13 (depends on 8) The low power oscillator circuit of claim 8 wherein the second delay circuit includes a series of inverters. ### Claim 14 An integrated circuit low power oscillator circuit for use in refreshing a DRAM comprising: a constant current source which is substantially independent of variations in a supply voltage Vcc and temperature, wherein the constant current source includes first and second p-channel transistors coupled between a first voltage connection and a second voltage connection; wherein the gate electrode of the first transistor is coupled to the source of the second transistor and the gate electrode of the second transistor is coupled to the drain of the first transistor; first and second resistors, wherein said first resistor is coupled between the drain of the first transistor and the first voltage connection and the second resistor is coupled between the source of the second transistor and the second voltage connection; and wherein the source of the first transistor is coupled to the second voltage connection and the drain of the second transistor outputs a constant current; a capacitor coupled to the constant current source to substantially establish the period of oscillation determined by the current generated by the constant current source; said constant current source and said capacitor forming a first delay circuit; a differential amplifier coupled to the capacitor to provide an output when the capacitor is charged to a certain voltage by the constant current source, said differential amplifier having transistors with long channel lengths to limit current loss from V.sub.CC to ground; a current limiting circuit coupled to said differential amplifier to limit current loss and power dissipation; a latch coupled to said current limiting circuit to provide a stable output; a second delay circuit including a series of inverters coupled to receive the output from said latch and provide an oscillating output pulse signal; and an electrical connection from the second delay circuit to said first delay circuit. ### Claim 15 A method of generating an oscillating output that consumes low power comprising the steps of: providing a substantially constant current using a low power current source; generating a controlled first delay based upon the constant current; generating a second delay based on a series of cascaded inversions; using an electrical signal that is generated subsequent to said first delay for generating further iterations of said controlled first delay; and outputting an oscillating signal, wherein a period of oscillation of said oscillating signal is substantially determined by said first delay. ### Claim 16 (depends on 15) The method of generating an oscillating output of claim 15 wherein the step of generating said first delay includes charging a capacitor to a certain voltage. ### Claim 17 (depends on 16) The method of generating an oscillating output of claim 16 wherein the step of generating said first delay further includes inputting the voltage of the charged capacitor to a differential amplifier to provide a high output when the voltage has reached a predetermined level. ### Claim 18 (depends on 9) The low power oscillator circuit according to claim 9 wherein the current limiting circuit comprises: a first inverting circuit having an input for receiving an input signal, a first output for outputting a first output signal and a second output for outputting a second output signal; a second inverting circuit coupled to said first inverting circuit, said second inverting circuit having first and second inputs for receiving said first and second output signals and having an output for outputting a third output signal. ### Claim 19 (depends on 18) The low power oscillator circuit of claim 18 wherein said first inverting circuit includes a first inverter and a second inverter, wherein said first inverter is coupled to receive said input signal and to output said first output signal, and wherein said second inverter is coupled to receive said input signal and to output said second output signal. ### Claim 20 (depends on 19) The low power oscillator circuit of claim 19 wherein each of said inverters includes a p channel transistor and an n channel transistor coupled between a first potential and a second potential. ### Claim 21 (depends on 20) The low power oscillator circuit of claim 20 wherein the first inverter further includes an n channel transistor coupled between the n channel transistor and the second potential and the second inverter further includes a p channel transistor coupled between the p channel transistor and the first potential. ### Claim 22 (depends on 18) The low power oscillator circuit of claim 18 further including a latch circuit coupled to the output of said second inverting circuit, said latch circuit comprising a first inverter and a second inverter, each inverter having an input and an output. ### Claim 23 (depends on 22) The low power oscillator circuit of claim 22 wherein the first inverter circuit includes an n channel and a p channel transistor coupled between a and a second potential, and coupled to receive the receive the output of the second inverter and wherein the input of the second inverter is coupled to receive the output of the first inverter. ### Claim 24 (depends on 23) The low power oscillator circuit of claim 23 wherein the first inverter further includes a p channel transistor coupled between the p channel transistor and the first potential and an n channel transistor coupled between the n channel transistor and the second potential. ### Claim 25 (depends on 1) The low power oscillator circuit of claim 1 further comprising: a control signal based on said second delay circuit, said control signal being controllingly coupled to said constant current source via said electrical connection. ### Claim 26 (depends on 25) The low power oscillator circuit of claim 25 wherein said constant current source includes: first, second, third and fourth transistors; connections to a first voltage and a second voltage; and first and second resistors; wherein said control signal is coupled to control the operation of said first and fourth transistors in complementary fashion so that when said first transistor is in an ON state, said second voltage is coupled therethrough and said fourth transistor is in an OFF state so that said first voltage is not coupled therethrough, and when said third transistor is in an OFF state, said fourth transistor is in an ON state; wherein a first circuit path is formed from series connections from said second voltage connection to said first transistor, first resistor, second transistor, and fourth transistor to said first voltage connection; wherein a second circuit path is formed from series connections from said second voltage connection to said first transistor, third transistor, and second resistor to said first voltage connection; wherein the gate electrode of the second transistor is coupled to a node in the second circuit path; wherein the gate electrode of the third transistor is coupled to another node in the first circuit path; wherein said second transistor selectively outputs a constant current to said charge storage device. ### Claim 27 (depends on 26) The circuit of claim 26 wherein said first and second resistors are on the order of about one megohm, whereby said constant current source consumes low power. ### Claim 28 (depends on 26) The circuit of claim 26 wherein said first, second, and third transistors are p-channel transistors and said fourth transistor is an n-channel transistor. ### Claim 29 (depends on 1) The oscillator circuit of claim 1 wherein said output pulse signal generated by said second delay circuit if substantially smaller than a delay generated by said first delay circuit; and wherein said first delay circuit consumes less power than said second delay circuit. ### Claim 30 (depends on 7) The oscillator circuit of claim 7 further comprising: a control signal base on an output of said second delay circuit, said control signal being controllingly coupled to said constant current source via said electrical connection; said constant current source further including third and fourth transistors, one being a p-channel transistor and the other being an n-channel transistor; said third transistor having one terminal coupled to said second voltage connection, another terminal coupled to said second resistor and said first transistor, and a control terminal responsively coupled to said control signal; said fourth transistor having one terminal coupled to said first voltage connection, another terminal coupled to said second transistor, and a control electrode responsively coupled to said control signal. ### Claim 31 (depends on 8) The oscillator circuit of claim 8 further comprising: a control signal based on an output of said second delay circuit; said control signal being coupled to said constant current source via said electrical connection; said constant current source being selectively enabled and disabled based on the state of said control signal. ### Claim 32 (depends on 31) The oscillator circuit of claim 31 wherein said constant current source includes first and second p-channel transistors coupled between a first voltage connection and a second voltage connection; wherein the gate electrode of the first transistor is coupled to the source of the second transistor and the gate electrode of the second transistor is coupled to the drain of the first transistor; first and second resistors, wherein said first resistor is coupled between the drain of the first transistor and the first voltage connection and the second resistor is coupled between the source of the second transistor and the second voltage connection; wherein the source of the first transistor is coupled to the second voltage connection and the drain of the second transistor outputs a constant current; third and fourth transistors, one being a p-channel transistor and the other being an n-channel transistor; said third transistor having one terminal coupled to said second voltage connection, another terminal coupled to said second resistor and said first transistor, and a control terminal responsively coupled to said control signal; said fourth transistor having one terminal coupled to said first voltage connection, another terminal coupled to said second transistor, and a control electrode responsively coupled to said control signal. ### Claim 33 (depends on 14) The oscillator circuit of claim 14 further comprising: a control signal based on an output of said second delay circuit, said control signal being controllingly coupled to said constant current source via said electrical connection; said constant current source further including third and fourth transistors, one being a p-channel transistor and the other being an n-channel transistor; said third transistor having one terminal coupled to said second voltage connection, another terminal coupled to said second resistor and said first transistor, and a control terminal responsively coupled to said control signal; said fourth transistor having one terminal coupled to said first voltage connection, another terminal coupled to said second transistor, and a control electrode responsively coupled to said control signal. ### Claim 34 (depends on 15) The method of claim 15 further comprising the step of providing a control signal based on said series of cascaded inversions and controlling said low power current source with said control signal via an electrical connection. ### Claim 35 (depends on 34) The method of generating an oscillating output of claim 34 wherein the step of providing a substantially constant current includes selectively coupling first and second current paths between first and second voltages, including: controlling a first transistor with said control signal so that said second voltage is applied to said first and second current paths; when said first transistor is turned ON, passing current through said first and second paths, including through a second transistor and a first resistor in said first path to a first node, and through a third transistor and a second resistor to said first voltage; controlling a fourth transistor in said first current path to be turned OFF when said first transistor is turned ON, thereby blocking current from passing to said first voltage via said fourth transistor, the method further including controlling said fourth transistor to be turned ON when said first transistor is turned OFF so that said first node is coupled to said first voltage. ### Claim 36 (depends on 1) The oscillator circuit of claim 1 wherein the power consumption of said first delay circuit is below about 11 microamperes. ### Claim 37 (depends on 7) The oscillator circuit of claim 7 wherein said first and second resistors have resistances on the order of about 1 megohm. ### Claim 38 A low power method of generating an oscillating signal for an integrated circuit comprising the steps of: using a first delay circuit for generating first pulses, including controlling the power consumption not to exceed about 11 microamperes; and using a second delay circuit to generate second pulses on said first pulses; wherein the first pulse has a period that is at lest one order of magnitude greater than a period of the second pulse. ### Claim 39 (depends on 38) The method of claim 38 wherein said step of using a first delay includes using a well-controlled delay circuit that is substantially independent of variations in a power supply voltage VCC and temperature. ### Claim 40 (depends on 7) The oscillator circuit of claim 7 wherein the power consumption of said first delay circuit is below about 11 microamperes.