# US 5,345,121 A · Differential amplification circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,345,121 A - Document ID: US5345121A - Status: Granted - Kind: A - Application number: 08/024,291 - Filed: 1993-03-01 - Granted: 1994-09-06 - Earliest claimed: 1992-02-27 - Assignees: Fujitsu Limited; Fukitsu VLSI Limited - Inventors: Eisaku Itoh - Web page: https://patentgrep.com/patent/US5345121A ## CPC - H03K 3/356165: {using additional transistors in the feedback circuit} - H03K 3/356069: {using additional transistors in the feedback circuit (H03K3/356104, H03K3/3562 take precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The sources of first and second N-channel MOS transistors are interconnected. A complementary input signal is inputted to the gates of the first and second N-channel MOS transistors, and a complementary output signal is outputted from their drains. Switch circuits are respectively connected between the source of the first or the second N-channel MOS transistors, and the interconnected sources of the first and second N-channel MOS transistors. Each switch circuit differs from the N-channel MOS transistor to which the switch circuit is connected. The opening and closing operations of the switch circuit are controlled, based on a complementary signal from the respective MOS transistor. ## Claims ### Claim 1 A differential amplification circuit comprising: a first N-channel MOS transistors having a source terminal, a drain terminal for outputting a first output signal, and a gate for receiving a first input signal; a second N-channel MOS transistor having a source terminal, a drain terminal for outputting a second output signal complementary to said first output signal, and a gate terminal for receiving a second input signal complementary to said first input signal; first switch means for connecting said source terminal of said first N-channel MOS transistor to a common potential point, in response to said second output signal; and second switch means for connecting said source terminal of said second N-channel MOS transistor to said common potential point, in response to said first output signal. ### Claim 2 (depends on 1) The differential amplification circuit according to claim 1, wherein said first and second switch means are similar in structure and function. ### Claim 3 (depends on 2) The differential amplification circuit according to claim 2, wherein when said first switch means connects the source of said first N-channel MOS transistor to said common potential point, said second switch means disconnects the source of said second N-channel MOS transistor from said common potential point, and wherein when said second switch means connects the source of said second N-channel MOS transistor to said common potential point, said first switch means disconnects the source of said first N-channel MOS transistor with said common potential point. ### Claim 4 (depends on 1) The differential amplification circuit according to claim 1, wherein the differential amplification circuit is a latch type sense amplifier further comprising: first and second P-channel MOS transistors, each having a drain, a source and a gate; and wherein the drains of said first and second N-channel MOS transistors are connected to the drains of said first and second P-channel MOS transistors, respectively, and the gates of said first and second P-channel MOS transistors are cross coupled to the drains of said second and first N-channel MOS transistors, respectively. ### Claim 5 (depends on 1) The differential amplification circuit according to claim 1, wherein said switch means comprises an inverter circuit which includes third and fourth P-channel MOS transistors and third and fourth P-channel MOS transistors and third and fourth N-channel MOS transistors, each of which includes a source, a drain and a gate; and wherein the sources of said third and fourth N-channel MOS transistors are interconnected, the drains of said third and fourth N-channel MOS transistors are connected to the sources of said first and second N-channel MOS transistors, respectively, and said complementary output signals are inputted to at least some of the gates of said inverter circuit. ### Claim 6 (depends on 5) The differential amplification circuit according to claim 5, further comprising: first and second short circuiting transistors connected between the sources of said first and second N-channel MOS transistors, and connected between the drains of said first and second N-channel MOS transistors, respectively, to cause a short therebetween. ### Claim 7 (depends on 6) The differential amplification circuit according to claim 6, wherein said first and second short circuiting transistors are NMOS transistors. ### Claim 8 (depends on 5) The differential amplification circuit according to claim 5, wherein each source of said third and fourth N-channel MOS transistors is connected to a gate transistor, for connection to a power source. ### Claim 9 (depends on 6) The differential amplification circuit according to claim 6, wherein each source of said third and fourth N-channel MOS transistors is connected to a gate transistor, for connection to a power source. ### Claim 10 A differential amplification circuit comprising: a first P-channel MOS transistor having a source terminal, a drain terminal for outputting a first output signal, and a gate terminal for receiving only a first input signal; a second P-channel MOS transistor having a source terminal, a drain terminal for outputting a second output signal complementary to said first output signal, and a gate terminal for receiving only a second input signal; first switch means for connecting said drain terminal of said first P-channel MOS transistor to a common potential point, in response to said second output signal; and said second switch means for connecting said drain terminal of said second P-channel MOS transistor to said common potential point, in response to said first output signal. ### Claim 11 (depends on 10) The differential amplification circuit according to claim 10, further comprising: first and second N-channel MOS transistors; and a latch type sense amplifier, wherein the drains of said first and second P-channel MOS transistors are connected to drains of said first and second N-channel MOS transistors, respectively; and wherein gates of said first and second N-channel MOS transistors are cross coupled to the gates of said second and first P-channel MOS transistors. ### Claim 12 (depends on 11) The differential amplification circuit according to claim 11, wherein said first and second switch means comprise: a CMOS type inverter including third and fourth P-channel MOS transistors and third and fourth N-channel MOS transistors each including a source, a gate and a drain; wherein the sources of said third and fourth N-channel MOS transistors are interconnected; and wherein the drains of said third and fourth N-channel MOS transistors are connected to the sources of said first and second N-channel MOS transistors, respectively.