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US 5,345,114 AGranted
Superconductor logic and switching circuits
OwnerQiyuan Ma, Walter N. Hardyinventors
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OwnerQiyuan Ma, Walter N. Hardyinventors
Estimating the term…
Current controlled superconductor switches formed by reactive patterning or other fabrication techniques may be used to form logic circuits including OR, AND, NOR, NAND, and NOT gates, a circuit breaker or an analog-to-digital converter. Each switch contains a superconductor resistor electrically connected in parallel with a non-superconductor resistor. The superconductor resistor has a critical current I.sub.c, such that it exhibits no electrical resistance to current flow less than I.sub.c, and exhibits positive electrical resistance to current flow greater than or equal to I.sub.c. The switch can accordingly be toggled between two states (i.e. superconducting and non-superconducting) by suitably controlling the current flowing through the switch. This switching behaviour provides the basis for constructing logic gates and other digital circuit devices.
A logic inverter gate comprising:
A logic "NOR" gate comprising:
A logic "NAND" gate comprising:
A circuit breaker for preventing a current I flowing through a circuit having an effective resistance r.sub.L from exceeding a critical current I.sub.c, said circuit breaker comprising:
An analog to digital converter for representing the magnitude of an input analog current signal I as a plurality of binary voltage signals V.sub.1, V.sub.2, . . . V.sub.n, each of said voltage signals corresponding to a selected magnitude portion of said analog signal, said analog to digital converter comprising a plurality of current controlled superconductor switches, each of said switches comprising a superconductor resistor electrically connected in parallel with a non-superconductor resistor, said superconductor resistor having a critical current I.sub.c, having no electrical resistance to current flow less than I.sub.c and having positive electrical resistance to current flow greater than or equal to I.sub.c, said switches being arranged in a plurality of tiers R.sub.1, R.sub.2, . . . R.sub.n with said first tier R.sub.1 comprising one of said switches, said second tier R.sub.2 comprising two of said switches electrically connected in parallel, said third tier R.sub.3 comprising three of said switches electrically connected in parallel, and each successive tier R.sub.i comprising an integer number i of said switches electrically connected in parallel, said tiers being electrically connected in series, whereby said voltage signal V.sub.1 is developed across said tier R.sub.1, V.sub.1 is larger than a first threshold value when I.gtoreq.I.sub.c, and V.sub.1 .apprxeq.0 when I<I.sub.c, said voltage signal V.sub.2 is developed across said tier R.sub.2, V.sub.2 is larger than said threshold value when I.gtoreq.2*I.sub.c, and V.sub.2 .apprxeq.0 when I<2*I.sub.c said voltage signal V.sub.3 is developed across said corresponding tier R.sub.3, V.sub.3 is larger than said threshold value when I.gtoreq.3*I.sub.c, and V.sub.3 .apprxeq.0 when I<3*I.sub.c and each successive tier R.sub.i develops a corresponding voltage signal V.sub.i which is larger than said threshold value when I.gtoreq.i*I.sub.c.
An analog to digital converter for representing the magnitude of an input analog current signal I as a plurality of binary voltage signals V.sub.1, V.sub.2, . . . V.sub.n, each of said voltage signals corresponding to a selected magnitude portion of said analog signal, said analog to digital converter comprising a plurality of superconductor resistors each having a critical current I.sub.c, having no electrical resistance to current flow less than I.sub.c and having positive electrical resistance to current flow greater than or equal to I.sub.c, said superconductor resistors being arranged in a plurality of tiers R.sub.1, R.sub.2, . . . R.sub.n with said first tier R.sub.1 comprising one of said superconductor resistors, said second tier R.sub.2 comprising two of said superconductor resistors electrically connected in parallel, said third tier R.sub.3 comprising three of said superconductor resistors electrically connected in parallel, and each successive tier R.sub.i comprising an integer number i of said superconductor resistors electrically connected in parallel, said tiers being electrically connected in series, whereby said voltage signal V.sub.1 is developed across said tier R.sub.1, V.sub.1 is greater than a first threshold value when I.gtoreq.I.sub.c, and V.sub.1 .apprxeq.0 when I<I.sub.c said digital voltage signal V.sub.2 is developed across said tier R.sub.2, V.sub.2 is greater than said first threshold value when I.gtoreq.2*I.sub.c, and V.sub.1 .apprxeq.0 when I<2*I.sub.c, said digital voltage signal V.sub.3 is developed across said corresponding tier R.sub.3, V.sub.3 is greater than said first threshold value when I.gtoreq.3*I.sub.c, and V.sub.3 .apprxeq.0 when I<3*I.sub.c, and each successive tier R.sub.i develops a corresponding digital voltage signal V.sub.i which is greater than said first threshold value when I.gtoreq.i*I.sub.c.
Dependencies are inferred from the claim text.