# US 5,344,790 A · Making integrated circuit transistor having drain junction offset

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- Number: US 5,344,790 A
- Document ID: US5344790A
- Status: Granted
- Kind: A
- Application number: 08/114,754
- Filed: 1993-08-31
- Granted: 1994-09-06
- Earliest claimed: 1993-08-31
- Assignees: SGS-Thomson Microelectronics S.A.
- Inventors: Frank R. Bryant; Robert L. Hodges
- Web page: https://patentgrep.com/patent/US5344790A

## CPC

- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6717: {the source and the drain regions being asymmetrical}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode. Due to the difference in diffusion rates between the relatively slow-diffusing dopant and the relatively fast-diffusing dopant, a transistor having a drain junction offset is formed.

## Claims

### Claim 1

A method for forming an integrated circuit device, comprising the steps of:
forming a gate insulating layer over a conductive layer;
forming a gate electrode over the gate insulating layer;
forming a source sidewall spacer and a drain sidewall spacer alongside opposite vertical edges of the gate electrode;
forming a mask over a drain region in the conductive layer;
implanting a relatively fast-diffusing dopant into a source region in the conductive layer;
removing the mask;
implanting a relatively slow-diffusing dopant into the drain region; and
annealing the conductive layer causing the relatively fast-diffusing dopant and the relatively slow-diffusing dopant to diffuse into the conductive layer, producing a drain junction offset in the integrated circuit device.

### Claim 2 (depends on 1)

The method of claim 1 wherein the conductive layer comprises monocrystalline silicon.

### Claim 3 (depends on 1)

The method of claim 1 wherein the conductive layer comprises polycrystalline silicon.

### Claim 4 (depends on 1)

The method of claim 1 wherein the relatively fast-diffusing dopant comprises boron, and wherein the relatively slow-diffusing dopant comprises indium.

### Claim 5 (depends on 1)

The method of claim 1 wherein the relatively fast-diffusing dopant comprises phosphorus, and wherein the relatively slow-diffusing dopant comprises arsenic.

### Claim 6 (depends on 1)

The method of claim 1 wherein the relatively fast-diffusing dopant comprises phosphorus, and wherein the relatively slow-diffusing dopant comprises antimony.

### Claim 7 (depends on 1)

The method of claim 1 wherein the relatively fast-diffusing dopant has an associated fast diffusion rate that is at least twice an associated slow diffusion rate associated with the relatively slow-diffusing dopant.

### Claim 8 (depends on 1)

The method of claim 1 wherein the step of implanting a relatively slow-diffusing dopant into the drain region further comprises implanting a relatively slow-diffusing dopant into the drain region and the source region.

### Claim 9 (depends on 1)

The method of claim 1 wherein the step of annealing the conductive layer causes the relatively fast-diffusing dopant to extend beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causes the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a distance that is less than approximately half the width of the drain sidewall spacer.