# US 5,344,786 A · Method of fabricating self-aligned heterojunction bipolar transistors

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- Number: US 5,344,786 A
- Document ID: US5344786A
- Status: Granted
- Kind: A
- Application number: 07/942,474
- Filed: 1992-09-09
- Granted: 1994-09-06
- Earliest claimed: 1990-08-31
- Assignees: Texas Instruments Incorporated
- Inventors: Burhan Bayraktaroglu
- Web page: https://patentgrep.com/patent/US5344786A

## CPC

- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 62/85: being Group III-V materials, e.g. GaAs
- Y10S 148/072: Heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A method of fabricating heterojunction bipolar transistors (HBTs) including epitaxial growth of collector, base and emitter layers, allowing for self-aligned emitter-base contacts to minimize series base resistance and to reduce total base-collector capacitance.

## Claims

### Claim 1

A method of fabricating a heterojunction bipolar transistor, comprising the steps of:
(a) forming a collector layer over a semi-insulating semiconductor substrate;
(b) forming a base layer over said collector layer;
(c) forming an emitter layer over said base layer;
(d) forming an ohmic emitter contact layer over said emitter layer;
(e) forming an insulator layer over said ohmic emitter contact layer;
(f) removing said insulator layer and said ohmic emitter contact layer from all areas not covering an emitter location;
(g) forming insulator sidewalls abutting vertical surfaces of said insulator layer and said ohmic emitter contact layer, said insulator sidewalls also abutting a portion of a horizontal surface of said emitter layer;
(h) removing said emitter layer from all areas not covered by said insulator layer or by said insulator sidewalls; and
(i) forming an ohmic base contact layer to be horizontally continuous over said insulator layer, said insulator sidewalls and a portion of said base layer, and to be vertically discontinuous between said insulator sidewalls and said portion of said base layer.

### Claim 2 (depends on 1)

The heterojunction bipolar transistor device fabrication method of claim 1, comprising the further step of:
(a) forming said emitter layer with a semiconductor material with a wider bandgap than said base layer semiconductor material.

### Claim 3 (depends on 1)

The heterojunction bipolar transistor device fabrication method of claim 1, comprising the further step of:
(a) forming said emitter layer with a semiconductor material with a wider bandgap than said collector layer semiconductor material.

### Claim 4 (depends on 1)

The heterojunction bipolar transistor device fabrication method of claim 1, comprising the further steps of:
(a) forming said collector layer with GaAs on a GaAs substrate;
(b) forming said base layer with GaAs; and
(c) forming said emitter layer with Al.sub.x Ga.sub.1-x As.

### Claim 5 (depends on 4)

The heterojunction bipolar transistor device fabrication method of claim 4, comprising the further steps of:
(a) doping said collector layer n-type;
(b) doping said base layer p-type; and
(c) doping said emitter layer n-type.

### Claim 6 (depends on 1)

The heterojunction bipolar transistor device fabrication method of claim 1, comprising the further step of:
(a) forming said emitter contact layer with AuGe/Ni/Au.

### Claim 7 (depends on 1)

The heterojunction bipolar transistor device fabrication method of claim 1, comprising the further step of:
(a) forming said emitter layer by epitaxial growth of in situ doped semiconductor material.

### Claim 8 (depends on 1)

The heterojunction bipolar transistor device fabrication method of claim 1, comprising the further step of:
(a) forming a metal ion mill mask layer on said insulator layer.

### Claim 9 (depends on 8)

The heterojunction bipolar transistor device fabrication method of claim 8, comprising the further step of:
(a) forming said metal ion mask layer with Ti.

### Claim 10 (depends on 8)

The heterojunction bipolar transistor device fabrication method of claim 8, including the further step of:
(a) removing said metal ion mill mask from regions not in an active area of said heterojunction bipolar transistor.

### Claim 11 (depends on 1)

The heterojunction bipolar transistor device fabrication method of claim 1, further including the step of:
(a) forming non-conductive regions by ion implantation in areas of said collector layer not beneath an emitter region.

### Claim 12 (depends on 1)

The heterojunction bipolar transistor device fabrication method of claim 1, comprising the further step of:
(a) forming said base layer by epitaxial growth of in situ doped semiconductor material.