Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate

A method of forming a complementary first and second transistor in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer superjacent the substrate, and a silicon device layer superjacent the buried insulating layer, the first and the second transistors formed in the silicon device layer such that the first transistor is dielectrically isolated from the second transistor, the method comprising the steps of:

• implanting an N doped buried conductor region in the device layer;
• implanting a P doped buried conductor region in the device layer;
• forming an epitaxial silicon layer superjacent the device layer, said epitaxial layer having a thickness of at least 2 microns, said epitaxial silicon layer having a dopant polarity;
• forming an N doped low resistance path between a surface of said epitaxial layer and said implanted N doped buried conductor region, and forming a P doped low resistance path between said surface of said epitaxial layer and said implanted P doped buried conductor region;
• forming a well in a portion of said epitaxial layer, said well superjacent at least one of said implanted N doped buried conductor region and said implanted P doped buried conductor region, said well having a doping polarity opposite that of said epitaxial silicon layer;
• forming a trench from said surface of said epitaxial layer down to the buried insulating layer, being disposed between said well and a remainder of said epitaxial layer so as to dielectrically isolate said well from said remainder of said epitaxial layer;
• and
• forming the first transistor in said well and the second transistor in said remainder of said epitaxial layer by implanting base regions in said well and in said remainder of said epitaxial layer of opposite polarities, and by forming emitter regions enclosed by said base regions.