# US 5,344,524 A · SOI substrate fabrication

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- Number: US 5,344,524 A
- Document ID: US5344524A
- Status: Granted
- Kind: A
- Application number: 08/085,422
- Filed: 1993-06-30
- Granted: 1994-09-06
- Earliest claimed: 1993-06-30
- Assignees: Honeywell Inc.
- Inventors: Kalluri R. Sharma; Michael S. Liu
- Web page: https://patentgrep.com/patent/US5344524A

## CPC

- H10P 90/1906: {Preparing SOI wafers}
- H10P 50/242: {of Group IV materials}
- H10P 90/1922: {using silicon etch back techniques, e.g. BESOI or ELTRAN}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10P 90/1914: {using bonding}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/021: {of air gaps}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/20: Air gaps
- Y10S 148/012: Bonding, e.g. electrostatic for strain gauges
- Y10S 438/97: Specified etch stop material
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A back-etch silicon-on-insulator SOI process that has a silicon handle wafer with an oxide layer bonded at room temperature to a silicon device wafer with an etch stop and silicon device layer. The surfaces that are bonded at room temperature are first conditioned to be hydrophilic. After bonding, the edges of the layers are sealed. The silicon device wafer, the etch-stop layer and the device layer are boron doped. Most of the silicon device wafer is ground away. Then, the remaining portion of the silicon device wafer and the etch stop layer are chemically etched away, thereby leaving a uniform layer of silicon device layer on the oxide layer of the silicon handle wafer. Because the bonding, grinding and selective etching are performed at room temperature, inter-diffusion of the boron between the various layers is prevented and thus permits the selective etching process to result in a nearly perfect silicon device layer in terms of an even-surfaced, defect-free and thin layer on the buried oxide layer of silicon handle wafer. The resulting SOI wafer is then annealed at a high temperature, prior to device processing.

## Claims

### Claim 1

A method for fabricating a silicon-on-insulator substrate, comprising:
forming an etch-stop layer on a silicon device wafer;
forming a device layer on the etch-stop layer;
forming a dielectric layer on a silicon handle wafer;
making exposed surfaces of the dielectric layer and the device layer hydrophilic;
bonding the device layer and the dielectric layer at the exposed surfaces to each other at room temperature;
removing the silicon device wafer; and
removing the etch-stop layer wherein said removing steps are performed at room temperature.

### Claim 2 (depends on 1)

The method of claim 1 further comprising sealing edges from the silicon device wafer to the silicon handle wafer subsequent to the bonding and prior to the removing of the silicon device wafer and the edge-stop layer.

### Claim 3 (depends on 2)

The method of claim 2 further comprising annealing the bonding of the device layer and the dielectric layer.

### Claim 4 (depends on 3)

The method of claim 3 wherein:
the removing of the silicon device wafer is effected by grinding and etching; and
the removing the of the etch-stop layer is effected by etching.

### Claim 5 (depends on 4)

The method of claim 4 wherein the forming of the dielectric layer is effected by thermally oxidizing a surface of the silicon handle wafer.

### Claim 6 (depends on 5)

The method of claim 5 wherein:
the etch-stop layer is a heavily doped single crystal layer; and
the device layer is a lightly doped single silicon layer.

### Claim 7 (depends on 6)

The method of claim 6 wherein:
the forming of the etch-stop layer is effected by epitaxial deposition; and
the forming of the device layer is effected by epitaxial deposition.

### Claim 8 (depends on 7)

The method of claim 7 wherein:
the device layer has a thickness at a value set between 0.01 and 2.0 microns; and
the device layer, subsequent to the removing of the etch-stop layer, has a surface variation within plus and minus 75 Angstroms.

### Claim 9 (depends on 8)

The method of claim 8 wherein:
the silicon device wafer is lightly doped (p.sup.-) with boron;
the etch-stop layer is heavily doped (p.sup.++) with boron and co-doped with germanium; and
the silicon device layer is lightly doped (p.sup.-) with boron.

### Claim 10 (depends on 9)

The method of claim 9 wherein:
the making exposed surfaces of the dielectric layer and the device layer hydrophilic, prior to bonding the surfaces to each other, is effected by cleaning the exposed surfaces with an RCA solution;
the removing of the silicon device wafer by etching is effected with an application of ethylene diamine and pyrocatechol; and
the removing of the etch-stop layer by etching is effected with an application of 1HF:3 HNO.sub.3 :8 HAc.

### Claim 11

A method for fabricating a silicon-on-insulator substrate, comprising:
oxidizing a surface of a silicon handle wafer, resulting in an oxidized surface on the silicon handle wafer;
epitaxially depositing a highly boron doped (p.sup.++) single crystal layer as an etch-stop layer on a surface of a silicon device wafer;
epitaxially depositing lightly boron doped (p.sup.-) silicon layer as a device layer on the etch-stop layer;
conditioning a first surface of the silicon device layer and the oxidized surface of the silicon handle wafer to be hydrophilic;
bonding, at room temperature, the first surface of the silicon device layer and the oxidized surface of the silicon handle wafer to each other, resulting in bonded surfaces;
sealing the bonded surfaces at a bond perimeter with a sealant;
removing a significant portion of the silicon device wafer by grinding;
etching away the remaining portion of the silicon device wafer;
etching away the etch-stop layer, to expose a second surface of the silicon device layer wherein said removing and etching steps are performed at room temperature; and
annealing the bonding of the first surface of the silicon device layer and the oxidized surface of the silicon handle wafer.

### Claim 12 (depends on 11)

The method of claim 11 wherein the resulting silicon device layer has a thickness at a value between 0.01 and 2.0 microns, with a surface variation of plus and minus 75 Angstroms.

### Claim 13 (depends on 12)

The method of claim 12 further comprising:
thermally forming an oxide on the second surface of the silicon device layer; and
removing the oxide on the second surface of the silicon device layer to make the silicon device layer thinner.

### Claim 14 (depends on 13)

The method of claim 13 wherein the conditioning of the first surface of the silicon device layer and the oxidized surface of the silicon handle wafer is effected by cleaning the first surface and the oxidized surface with an RCA solution.

### Claim 15 (depends on 14)

The method of claim 14 wherein:
the remaining portion of the silicon device wafer, that is etched away, has a thickness between twenty and fifty microns; and
the etch-stop layer has a thickness of about two microns.

### Claim 16 (depends on 14)

The method of claim 14 wherein the annealing of the bonding of the first surface of the silicon device layer and the oxidized surface of the silicon handle wafer is performed at approximately 1000 degrees Centigrade for improved bond strength between the bonded surfaces of the silicon device layer and the silicon handle wafer.

### Claim 17 (depends on 15)

The method of claim 15 wherein:
the silicon device wafer has a boron concentration of approximately 10.sup.15 atoms/cm.sup.3 ;
the etch-stop layer has a boron concentration of approximately 10.sup.20 atoms/cm.sup.3 ; and
the silicon device layer has a boron concentration less than 10.sup.15 atoms/cm.sup.3.

### Claim 18 (depends on 17)

The method of claim 17 wherein the etch-stop layer is co-doped with about ten percent germanium, to compensate tensile stress caused by small boron atoms with compressive stress caused by larger germanium atoms.

### Claim 19 (depends on 18)

The method of claim 18 wherein:
the remaining portion of the silicon device wafer, that is etched away, is etched with ethylene diamine and pyrocatechol (EDP); and
the etch-stop layer, that is etched, is etched away with 1HF:3 HNO.sub.3 :8 HAc etchant.