Dense vertical programmable read only memory cell structure and processes for making them

In an electrically programmable memory device including an electrically conductive floating gate having a given surface area positioned over at least a portion of a channel region in a substantially planar surface of a semiconductor substrate between source and drain diffusions therein and insulated from the substrate surface by a gate dielectric layer therebetween, and an electrically conductive control gate having a surface area capacitively coupled through a control gate dielectric layer to an opposing surface area of said floating gate, an electrically conductive erase gate that is capacitively coupled with said floating gate through a layer of erase gate dielectric, said floating gate being characterized by controlling the amount of conduction in said at least a portion of channel region in proportion to the floating gate electrical potential level, the improvement wherein at least thirty-five percent of the opposing surface areas of said floating and control gates constituting said capacitive coupling are oriented substantially perpendicular to said substrate surface and extend away therefrom in a region of said floating gate given surface area, whereby an amount of area of said substrate that is occupied by said memory device is minimized, wherein said erase gate is positioned adjacent said substrate surface outside of said channel region and capacitively coupled thereto through an erase gate dielectric layer, thereby to serve as a field plate to electrically isolate said device from other devices on said substrate, and wherein said floating gate given surface area extends over only a portion of the distance between the source and drain diffusions and said control gate extends the rest of the distance therebetween over the channel region with the gate dielectric layer therebetween, whereby said device is a split channel type of memory cell.

In an electrically programmable memory device including an electrically conductive floating gate having a given surface area positioned over at least a portion of a channel region in a substantially planar surface of a semiconductor substrate between source and drain diffusions therein and insulated from the substrate surface by a gate dielectric layer therebetween, and an electrically conductive control gate having a surface area capacitively coupled through a control gate dielectric layer to an opposing surface area of said floating gate, an electrically conductive erase gate that is capacitively coupled with said floating gate through a layer of erase gate dielectric, said floating gate being characterized by controlling the amount of conduction in at least a portion of channel region in proportion to the floating gate electrical potential level, the improvement wherein at least thirty-five percent of the opposing surface areas of said floating and control gates constituting said capacitive coupling are oriented substantially perpendicular to said substrate surface and extend away therefrom in a region of said floating gate given surface area, whereby an amount of area of said substrate that is occupied by said memory device is minimized, wherein said erase gate is positioned adjacent an edge of said floating gate displaced from said substrate, and wherein said floating gate given surface area extends over only a portion of the distance between the source and drain diffusions and said control gate extends the rest of the distance therebetween over the channel region with the gate dielectric layer therebetween, whereby said device is a split channel type of memory cell.

A memory device cell, comprising:

• a semiconductor substrate having source and drain diffusions spaced a distance apart in one substantially planar surface thereof,
• an isolation dielectric layer carried by said substrate surface,
• a trench with opposing sidewalls formed through the isolation dielectric layer to said substrate surface but substantially not into said substrate surface, said trench being oriented with a length extending between said source and drain diffusions, having a width between sidewalls that is substantially perpendicular to said length, and having a depth that is substantially equal to at least one-half the width in the vicinity of said substrate;
• a gate dielectric layer carried by said substrate surface within said trench,
• an electrically conductive floating gate structure positioned on said gate dielectric layer with the trench in a manner to be capacitively coupled with said substrate for at least a portion of the trench length between the source and drain diffusions, said floating gate extending from the gate dielectric layer along said sidewalls and extending out of the trench to terminate in edges on a side of the isolation dielectric layer that is furthest displaced from the substrate, and
• an electrically conductive control gate positioned within said trench and having a surface area thereof separated from a corresponding surface area of said floating gate by a control gate dielectric layer in a manner to provide capacitive coupling between the floating and control gates, at least thirty-five percent of said coupling area occurring in surfaces within said trench that are oriented substantially orthogonal to said substrate surface.

A memory device cell, comprising:

• a semiconductor substrate having source and drain diffusions spaced a distance apart in one substantially planar surface thereof,
• an isolation dielectric layer carried by said substrate surface,
• a trench formed through the isolation dielectric layer to said substrate surface but substantially not into said substrate surface, said trench being oriented with a length extending between said source and drain diffusions, having a width substantially perpendicular to said length, and having a depth that is substantially equal to at least one-half the width in the vicinity of said substrate,
• a gate dielectric layer carried by said substrate surface within said trench,
• an electrically conductive floating gate structure positioned on said gate dielectric layer within the trench in a manner to be capacitively coupled with said substrate for at least a portion of the trench length between the source and drain diffusions,
• an electrically conductive control gate positioned within said trench and having a surface area thereof separated from a corresponding surface area of said floating gate by a control gate dielectric layer in a manner to provide capacitive coupling between the floating and control gates, at least thirty-five percent of said coupling area occurring in surfaces within said trench that are oriented substantially orthogonal to said substrate surface, and
• an electrically conductive erase gate capacitively coupled with the floating gate through an erase gate dielectric layer adjacent a surface of the isolation dielectric that is substantially parallel with and furthest displaced from said substrate surface.

A memory device cell, comprising:

• a semiconductor substrate having source and drain diffusions spaced a distance apart in one substantially planar surface thereof,
• an isolation dielectric layer carried by said substrate surface,
• a trench formed through the isolation dielectric layer to said substrate surface but substantially not into said substrate surface, said trench being oriented with a length extending between said source and drain diffusions, having a width substantially perpendicular to said length, and having a depth that is substantially equal to at least one-half the width in the vicinity of said substrate,
• a gate dielectric layer carried by said substrate surface within said trench,
• an electrically conductive floating gate structure positioned on said gate dielectric layer within the trench in a manner to be capacitively coupled with said substrate for at least a portion of the trench length between the source and drain diffusions,
• an electrically conductive control gate positioned within said trench and having a surface area thereof separated from a corresponding surface area of said floating gate by a control gate dielectric layer in a manner to provide capacitive coupling between the floating and control gates, at least thirty-five percent of said coupling area occurring in surfaces within said trench that are oriented substantially orthogonal to said substrate surface, and
• an electrically conductive erase gate buried within the isolation dielectric layer and separated from the substrate surface by a gate dielectric layer in a manner to be capacitively coupled with the substrate therethrough, said erase gate additionally being positioned adjacent the floating gate with an erase gate dielectric layer therebetween.

A memory device cell, comprising:

• a semiconductor substrate having source and drain diffusions spaced a distance apart in one substantially planar surface thereof,
• an isolation dielectric layer carried by said substrate surface,
• a trench formed through the isolation dielectric layer to said substrate surface but substantially not into said substrate surface, said trench being oriented with a length extending between said source and drain diffusions, having a width substantially perpendicular to said length, and having a depth that is substantially equal to at least one-half the width in the vicinity of said substrate,
• a gate dielectric layer carried by said substrate surface within said trench,
• an electrically conductive floating gate structure positioned on said gate dielectric layer within the trench in a manner to be capacitively coupled with said substrate for at least a portion of the trench length between the source and drain diffusions,
• an electrically conductive control gate positioned within said trench and having a surface area thereof separated from a corresponding surface area of said floating gate by a control gate dielectric layer in a manner to provide capacitive coupling between the floating and control gates, at least thirty-five percent of said coupling area occurring in surfaces within said trench that are oriented substantially orthogonal to said substrate surface, and
• an electrically conductive erase gate positioned within said isolation dielectric layer adjacent said trench and having an edge thereof separated from the floating gate by a layer of erase gate dielectric.

An array of a plurality of memory device cells, comprising:

• a semiconductor substrate having a substantially planar surface,
• a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,
• a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,
• a layer of gate dielectric on said substrate surface within the trenches,
• a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween, said floating gates extending from the gate dielectric layer of their respective trenches and extending out of the trench to terminate on either side thereof in edges positioned on a surface of the isolation dielectric layer furthest displaced from the substrate, and
• a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench.

An array of a plurality of memory device cells, comprising:

• a semiconductor substrate having a substantially planar surface,
• a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,
• a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,
• a layer of gate dielectric on said substrate surface within the trenches,
• a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,
• a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench, and
• a plurality of spaced apart, substantially parallel and elongated erase gates with their lengths extending in said second direction and positioned atop said isolation dielectric layer with a capacitive coupling with a top edge of said floating gate through an erase gate dielectric layer.

An array of a plurality of memory device cells, comprising:

• a semiconductor substrate having a substantially planar surface,
• a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,
• a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,
• a layer of gate dielectric on said substrate surface within the trenches,
• a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,
• a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench,
• wherein the portions of the floating gates formed against opposing trench sidewalls extend further away from said substrate than said control gate, and
• an erase gate formed atop said isolation dielectric and extending substantially continuously over an area including a plurality of floating gates in one or more trenches.

An array of a plurality of memory device cells, comprising:

• a semiconductor substrate having a substantially planar surface,
• a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,
• a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,
• a layer of gate dielectric on said substrate surface within the trenches,
• a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,
• a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench, and
• a plurality of spaced apart, substantially parallel and elongated erase gates with their lengths extending in said second direction and positioned within said isolation dielectric layer between trenches in a manner to be capacitively coupled through an erase gate dielectric with the floating gates in trenches on opposite sides thereof and capacitively coupled with the substrate through a gate dielectric layer, thereby to provide field plate isolation of the devices in said second direction.

An array of a plurality of memory device cells, comprising:

• a semiconductor substrate having a substantially planar surface,
• a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,
• a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,
• a layer of gate dielectric on said substrate surface within the trenches,
• a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,
• a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench, and
• a plurality of spaced apart, substantially parallel and elongated electrically conductive erase gates with their lengths extending in said second direction and positioned between said trenches with sidewall edges thereof being capacitively coupled to a sidewall of said floating gate through an erase gate dielectric layer therebetween.

An array of a plurality of memory device cells, comprising:

• a semiconductor substrate having a substantially planar surface,
• a plurality of spaced apart, substantially parallel and elongated source and drain diffusions formed in said substrate surface with their lengths extending in a first direction across the substrate,
• a layer of isolation dielectric covering said substrate surface and having a plurality of spaced apart, substantially parallel and elongated trenches therethrough to said substrate surface but substantially without extending into said substrate surface, said trenches oriented with their lengths extending in a second direction across the substrate, said first and second directions being substantially orthogonal to each other,
• a layer of gate dielectric on said substrate surface within the trenches,
• a plurality of floating gates formed in said trenches on said gate dielectric layer and spaced apart along the length of the trenches with one floating gate positioned between adjacent source and drain diffusions in a manner to be capacitively coupled to a substrate surface channel region therebetween,
• a control gate positioned at least partially in each of said plurality of trenches and extending along its length past at least several floating gates therein in a manner to form areas of capacitive coupling between the control gate and each of said at least several floating gates through a control gate dielectric layer, at least thirty-five percent of said areas of capacitive coupling being oriented substantially orthogonally to said substrate surface and within the trench, and
• wherein the trenches in the isolation dielectric layer include spacers formed on opposite sidewalls in a manner to gradually slope the sidewalls inward toward each other as they get closer to the substrate, thereby narrowing an effective width of the channel regions.

In an electrically programmable memory device including an electrically conductive floating gate having a given surface area positioned over at least a portion of a channel region in a substantially planar surface of a semiconductor substrate between source and drain diffusions therein and insulated from the substrate surface by a gate dielectric layer therebetween, an electrically conductive control gate having a surface area capacitively coupled through a dielectric layer to an opposing surface area of said floating gate, said floating gate being characterized by controlling the amount of conduction in said at least a portion of channel region in proportion to the floating gate electrical potential level, and an electrically conductive erase gate that is capacitively coupled with said floating gate through a layer of erase dielectric, the improvements wherein at least thirty-five percent of the opposing surface areas of said floating and control gates constituting said capacitive coupling are oriented substantially perpendicular to said substrate surface and extend away therefrom in a region of said floating gate given surface area, whereby an amount of area of said substrate that is occupied by said memory device is minimized, and wherein said erase gate is positioned adjacent said substrate surface outside of said channel region and capacitively coupled thereto through a dielectric layer, thereby to serve as a field plate to electrically isolate said device from other devices on said substrate.