US 5,341,120 AGranted

Comparison circuit

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorToyokatsu Nakajima

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Abstract

An analog input is compared with a comparison value by an analog comparator to set a comparison result register and comparison is automatically repeated until the value of the register coincides with the value of an expected value storing register. When the both values coincide with each other, an interrupt request signal is outputted and comparison is completed.

Claims8

Dependent claims

A comparison circuit for setting an interrupt request signal provided to a CPU, comprising:

an analog comparator, coupled to receive a comparison value, an external analog input signal characterized by a magnitude value, and a comparison control signal, for comparing, when said comparison control signal is asserted, the comparison value with the magnitude value of the external analog input signal and for setting a comparator output signal when the magnitude value of the external analog input signal coincides with the comparison value;
a comparison result register, coupled to receive the output of said analog comparator and to receive a latching signal, for latching the output of the analog comparator when the latching signal is set;
a control circuit for controlling the analog comparator and comparison result register, wherein said control circuit comprises:
a timer, coupled to receive a clock signal, for dividing the clock signal into constant cycles and providing a timer output signal defining said constant cycles;
an expected value storing register for storing an expected value;
an output comparator, coupled to said expected value storing register to receive said expected value and to said comparison result register to receive the comparator output signal latched therein, for setting the interrupt request signal provided to the CPU when the comparator output signal latched in said comparison result register coincides with the expected value stored by said expected value storing register;
and
means, coupled to receive said interrupt request signal, said timer output signal and coupled to control said analog comparator and comparison result register, for setting said comparison control signal and said latching signal in response to said timer output signal every constant cycle when said interrupt signal is not set so that comparison circuit repeatedly compares the input signal magnitude value and comparison value until both values coincide without requiring control by the CPU.

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Dependencies are inferred from the claim text.

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Abstract

A comparison circuit for setting an interrupt request signal provided to a CPU, comprising:

an analog comparator, coupled to receive a comparison value, an external analog input signal characterized by a magnitude value, and a comparison control signal, for comparing, when said comparison control signal is asserted, the comparison value with the magnitude value of the external analog input signal and for setting a comparator output signal when the magnitude value of the external analog input signal coincides with the comparison value;
a comparison result register, coupled to receive the output of said analog comparator and to receive a latching signal, for latching the output of the analog comparator when the latching signal is set;
a control circuit for controlling the analog comparator and comparison result register, wherein said control circuit comprises:
a timer, coupled to receive a clock signal, for dividing the clock signal into constant cycles and providing a timer output signal defining said constant cycles;
an expected value storing register for storing an expected value;
an output comparator, coupled to said expected value storing register to receive said expected value and to said comparison result register to receive the comparator output signal latched therein, for setting the interrupt request signal provided to the CPU when the comparator output signal latched in said comparison result register coincides with the expected value stored by said expected value storing register;
and
means, coupled to receive said interrupt request signal, said timer output signal and coupled to control said analog comparator and comparison result register, for setting said comparison control signal and said latching signal in response to said timer output signal every constant cycle when said interrupt signal is not set so that comparison circuit repeatedly compares the input signal magnitude value and comparison value until both values coincide without requiring control by the CPU.

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