Method for forming enhanced capacitance stacked capacitor structures using hemi-spherical grain polysilicon

A process for fabricating a DRAM container storage capacitor on a silicon substrate, said process comprising the steps of:

• forming parallel conductive lines on said substrate;
• forming a conductive plug between said pair of neighboring parallel conductive lines;
• forming a first planarized insulating layer over said parallel conductive lines and said conductive plug;
• forming a planarized second insulating layer over said first planarized insulative layer;
• forming an opening into said second insulating layer and said first insulating layer to expose an upper surface of said conductive plug;
• forming multiple layers of amorphous silicon into said opening and forming multiple silicon interfacing layers at the silicon grain boundaries, thereby separating each said silicon layer with an oxide layer;
• forming individual container structures having inner and outer surfaces and thereby exposing said second insulating layer;
• removing said second insulating layer thereby exposing said outer surface of said container structures;
• converting said exposed inner and outer surfaces of amorphous silicon into hemispherical grained polysilicon by subjecting said structures to a high vacuum anneal;
• forming a third insulating layer adjacent and coextensive said conductive container structure;
• and
• forming a second conductive layer superjacent and coextensive said third insulating layer.

A process for fabricating a DRAM container storage capacitor on a silicon substrate, said process comprising the steps of:

• forming parallel conductive lines on said substrate;
• forming a conductively doped polysilicon plug between said pair of neighboring parallel conductive word lines;
• forming a planarized tetra-ethyl-ortho-silicate (TEOS) insulating layer over said parallel conductive word lines and said plug;
• forming a planarized borophosphosilicate glass (BPSG) insulating layer over said planarized tetra-ethyl-ortho-silicate (TEOS) insulative layer;
• forming an opening into both insulating layers to expose an upper surface of said plug;
• forming first, second and third layers of conductively doped amorphous silicon in said opening and forming multiple silicon interfacing layers at the silicon grain boundaries, thereby separating each said conductively doped amorphous silicon layer with an oxide layer;
• forming individual container structures having inner and outer surfaces and thereby exposing said BPSG insulating layer;
• removing said BPSG insulating layer thereby exposing said outer surface of said container structures;
• converting said exposed inner and outer surfaces of amorphous silicon into hemispherical grained polysilicon by subjecting said structures to a high vacuum anneal;
• forming a nitride insulating layer adjacent and coextensive said conductive container structure;
• and
• forming a second conductively doped polysilicon layer superjacent and coextensive said nitride insulating layer.