High speed sample and hold circuit and radio constructed therewith

A high speed sample and hold circuit comprising:

• a sampling switch having an input for receiving a signal to be sampled and having an output;
• a hold capacitor coupled to said sampling switch output;
• a first transistor configured in a common drain circuit arrangement, having a gate coupled to said sampling switch output and having a source;
• a second transistor having a drain and a source, said second transistor configured as a substantially constant current source, said second transistor being coupled to said source of said first transistor, wherein said sampling switch, hold capacitor, first transistor and second transistor each reside within a common integrated circuit;
• a first resistor residing within said common integrated circuit and being coupled between said source of said first transistor and said drain of said second transistor;
• a second resistor residing within said common integrated circuit and being coupled to said source of said second transistor;
• a first external contact of said common integrated circuit coupled to said source of said first transistor;
• and
• a second external contact of said common integrated circuit coupled to said drain of said second transistor.

In a system comprising a sampling switch, a hold capacitor and a buffer amplifier, wherein:

• said sampling switch comprises an input for receiving a signal to be sampled, an output and a sampling signal input port coupled to a pulse generator for receiving a stream of pulses at a sampling rate;
• said hold capacitor is coupled to said sampling switch output;
• and
• said buffer amplifier comprises a first transistor configured in a common drain circuit arrangement, having a gate coupled to said output of said sampling switch and having a source and a drain, and a second transistor having a drain and a source, said second transistor being configured as a constant current source coupled via a first resistor exhibiting a first resistance coupled between said source of said first transistor and said drain of said second transistor, a second resistor coupled to said source of said second transistor, said second resistor exhibiting a second resistance which substantially equals said first resistance, a first terminal for receiving a relatively positive voltage, said first terminal coupled to said first transistor drain, a second terminal for receiving a relatively negative voltage, said second terminal coupled to said second transistor source via said second resistor,
• a method for generating an IF signal exhibiting an IF frequency, said method comprising steps of:
• supplying an RF signal exhibiting an RF period to said input of said sampling switch;
• successively sampling, in response to said stream of pulses coupled to said sampling signal input port, said RF signal by said sampling switch to generate a stream of RF samples, said sampling rate causing less than one sample to be taken per RF period, and said sampling occurring for each sample over a duration which is substantially less than said RF period;
• and
• holding by said hold capacitor, each of said RF samples between successive ones of said samples.