Interconnection network and crossbar switch for the same
AssigneeHitachi, Ltd.
InventorsAkira Muramatsu, Ikuo Yoshihara, Kazuo Nakao, Takehisa Hayashi, Teruo Tanaka, Shigeo Nagashima
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AssigneeHitachi, Ltd.
InventorsAkira Muramatsu, Ikuo Yoshihara, Kazuo Nakao, Takehisa Hayashi, Teruo Tanaka, Shigeo Nagashima
Estimating the term…
In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates (i.sub.1, i.sub.2, - - - , n.sub.k-1, n.sub.k+1, - - - , i.sub.N) of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).
A computer implemented method for asynchronously selecting a communication interconnection path among a plurality of processor elements wherein each of the processor elements are identified by a coordinate set and wherein the processor elements are communicatively connected by a plurality of coordinate transforming crossbar switches, comprising steps of:
A computer implemented system for asynchronously selecting a communication interconnection path among a plurality of processor elements wherein each of the processor elements are identified by a coordinate set and wherein the processor elements are communicatively connected by a plurality of coordinate transforming crossbar switches, comprising:
Dependencies are inferred from the claim text.