Interface circuit for interfacing a peripheral device with a microprocessor operating in either a synchronous or an asynchronous mode

An interface circuit for interfacing a peripheral device and a microprocessor to enable data transference between a microprocessor data bus and a memory location within the peripheral device, the interface circuit comprising:

• means for selecting an operating mode for the interface circuit, the operating mode being one of a synchronous mode and an asynchronous mode, whereby the interface circuit is operated in a synchronous mode when the microprocessor utilizes synchronous bus control and in an asynchronous mode when the microprocessor utilizes asynchronous bus control;
• means for receiving a request from the microprocessor for access to a peripheral memory location, the request including a select signal for selecting the peripheral device for access, an address signal specifying the peripheral memory location, and a read/write signal for indicating whether the request is for a read access or a write access;
• means for receiving a clock signal from the microprocessor;
• means for latching the address signal and for sending a corresponding latched address signal to the peripheral device;
• a temporary data storage register for temporarily storing data received from the microprocessor and the peripheral device;
• means for coupling the microprocessor data bus and the temporary data storage register for transferring data between the microprocessor data bus and the temporary data storage register;
• means for coupling the peripheral device and the data storage register for transferring data between the data storage register and the peripheral memory location;
• means for receiving a busy signal from the peripheral device indicating when the peripheral device is engaged in data transference between the temporary data storage register and the peripheral memory location;
• and
• control means responsive to the interface operating mode, the clock signal, the select signal, the read/write signal, and the busy signal for separately timing and controlling (A) data transference between the microprocessor data bus and the temporary data storage register, and (B) data transference between the temporary data storage register and the peripheral memory location.

An interface circuit for interfacing a peripheral device and a microprocessor to enable data transference between a microprocessor data bus and a memory location within the peripheral device, the interface circuit comprising:

• means for selecting an operating mode for the interface circuit, the operating mode being one of a synchronous mode and an asynchronous mode, whereby the interface circuit is operated in a synchronous mode when the microprocessor utilizes synchronous bus control and in an asynchronous mode when the microprocessor utilizes asynchronous bus control;
• means for receiving a request from the microprocessor for access to a peripheral memory location, the request including a select signal for selecting the peripheral device for access, an address signal specifying the peripheral memory location, and a read/write signal for indicating whether the request is for a read access or a write access;
• means for receiving a clock signal from the microprocessor;
• means for latching the address signal and for sending a corresponding latched address signal to the peripheral device;
• a temporary data storage register for temporarily storing data received from the microprocessor and the peripheral device;
• means coupled the peripheral device and the temporary data storage register for transferring multiple bytes of data in parallel between the temporary data storage register and the peripheral memory location;
• means for coupling the microprocessor data bus and the temporary data storage register for separately transferring single bytes of data between the microprocessor data bus and the temporary data storage register;
• means for receiving a busy signal from the peripheral device indicating when the peripheral device is engaged in transferring multiple bytes of data between the temporary data storage register and the peripheral memory location;
• and
• control means responsive to the interface operating mode, the clock signal, the select signal, the read/write signal, and the busy signal for separately timing and controlling multiple transference of single byte data between the microprocessor data bus and the temporary data storage register, and multiple byte data transference between the temporary data storage register and the peripheral memory location.