Synchronous dynamic random access memory
AssigneeOki Electric Industry Co., Ltd.
InventorAtsushi Takasugi
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Abstract
A synchronous dynamic random-access memory has transparent latch circuits that latch address signals in synchronization with a clock signal. An X-address is latched following activation of a first control signal; a Y-address is latched following activation of a second control signal. Data selected by the latched X- and Y-addresses are held in a data latch and output through a tri-state output circuit in synchronization with the clock signal. Data output starts a certain number of clock cycles from activation of the first control signal. The data can be output for one clock cycle, the same data can be output for two or more consecutive clock cycles, or different data can be output in consecutive clock cycles in an order determined by certain bits in the X- and Y-addresses.
Claims6
A synchronous dynamic random-access memory that provides data output in response to multiplexed address signals, a first control signal, a second control signal, and a clock signal, comprising:
- a memory cell array having a plurality of memory cells;
- an address input circuit for latching said address signals on a first transition of said clock signal selected by said first control signal to generate an X-address, and on a second transition of said clock signal selected by said second control signal to generate a Y-address;
- a decoding circuit coupled to said memory cell array and said address input circuit, for selecting at least one memory cell in said memory cell array according to said X-address and said Y-address;
- and
- an output circuit coupled to said memory cell array, for outputting data from said memory cells in synchronization with said clock, wherein said output circuit comprises:
- a multiple data latch circuit for simultaneously latching data read from a plurality of said memory cells;
- a consecutive output control circuit for selecting data latched in said multiple data latch circuit, different data being selected in different clock cycles;
- and
- a tri-state output circuit for externally outputting data selected by said consecutive output control circuit.
Dependencies are inferred from the claim text.