US 5,337,285 AGranted

Method and apparatus for power control in devices

AssigneeRambus Inc.

InventorsFrederick A. Ware, James A. Gasbarro, John B. Dillon, Matthew M. Griffin, Richard M. Barth, Mark A. Horowitz

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Abstract

A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provided to control the clock input to the component. In a standby state, the clock signal is not provided to the component but the PLL/DLL continues to operate, driving the dummy load. Thus, when it is desirable to power on the circuit, the standby latch is reset and the clock signal is provided to the component, thereby turning on the component with little latency.

Claims36

Dependent claims

A component comprising memory and logic which, when driven by a clock signal, consumes power, said component receiving an external clock signal, said component comprising circuitry to decrease the power consumption of the component when the component is not in use, said circuitry comprising:

a timing generator for receiving the external clock and generating an internal clock signal synchronized to the external clock;
at least one first logic gate means which receives as input a standby signal and the internal clock signal;
a feedback loop which receives the external clock signal, and drives a dummy clock load proportional to at least one clock load of the memory and logic of the component, said feedback loop coupled back to the timing generator to provide the internal clock signal feedback needed to operate the timing generator;
at least one standby latch receiving as input a first power control signal of a first state to reduce the power of at least a portion of the component, said latch upon receipt of the first power control signal generating the standby signal for input to the first logic gate means, such that the clock signal is not input to at least a portion of the memory and logic of the component, shutting down operation of at least a portion of the memory and logic and therefore the power consumed by the memory and logic, said standby latch upon receipt of a second power control signal, generating the standby signal of a second state which enables the internal clock signal to drive the memory and logic to operate;
wherein the operation of the timing generator is unaffected by the standby mode due to the feedback loop driving the dummy clock load, such that minimal latency is incurred switching in and out of standby mode.

2 more elements

a timing generator means for receiving the external clock signal and generating an internal clock signal synchronized to the external clock, said timing generator means driven by a current input;
a first logic gate means which receives as input the internal clock signal;
a feedback loop which receives the external clock signal and drives a dummy clock load proportional to at least one clock load of the memory and logic of the component, said feedback loop coupled back to the timing generator means to provide the internal clock signal feedback needed to operate the timing generator means;
a power down latch receiving as input a first power control signal, said power down latch upon receipt of the first power control signal disabling operation of the feedback loop such that the internal clock signal is not generated by the timing generator means;
control means coupled to receive a second power control signal and coupled to the power down latch such that when the second power control signal is received, a reset signal is asserted on the power down latch which enables the feedback loop to enable the timing generator means to begin generating an internal clock signal.

2 more elements

a timing generator means for receiving the external clock signal and generating an internal clock signal synchronized to the external clock, said timing generator means driven by a current input;
a first logic gate means which receives as input the internal clock signal;
a feedback loop which receives the external clock signal and drives a dummy clock load proportional to at least one clock load of the memory and logic of the component, said feedback loop coupled back to the timing generator means to provide the internal clock signal feedback needed to operate the timing generator means;
a low latency power down latch receiving as input a power down signal and reset signal, wherein upon receipt of the power down signal, said latch disabling the operation of the feedback loop such that a clock signal is not generated by the timing generator means, and upon receipt of the reset signal, said latch enables the feedback loop and the timing generator means to begin generating an internal clock signal;
and
control means coupled to receive a first power control signal and second power control signal, said control means upon receipt of the first power control signal issuing a power down signal to power down the timing generator means, and upon receipt of the second power control signal, said control means issuing a reset signal to reinitiate operation of the timing generator means;
wherein the first and second power control signals can be asserted to periodically restart the timing generator means.

4 more elements

In a component comprising memory and logic which when driven by a clock signal consumes power, said component receiving an external clock signal, a method to decrease the power consumption of the component when the component is not in use, comprising the steps of:

receiving an external clock signal and generating an internal clock signal synchronized to the external clock signal, said internal clock signal driving the component;
feeding back the internal clock signal to drive a dummy clock load proportional to at least one clock load of the memory and logic of the component and provide feedback information to maintain the internal clock signal synchronous with the external clock signal;
issuing a first power control signal of a first state to reduce the power of at least a portion of the component;
inhibiting the internal clock signal from driving at least a portion of the memory and logic of the component when the first power control signal is issued, wherein the internal clock signal continues to be generated based upon the external clock signal and fed back internal clock signal driving a dummy clock load;
and
when a second power control signal is issued, enabling the internal clock signal to drive the at least a portion of the memory and logic of the component;
wherein minimal latency is incurred controlling the power consumption of the component.

4 more elements

Dependencies are inferred from the claim text.