Squaring circuit for binary numbers

A squaring circuit for raising to the second power a first binary number X of n bits, each bit having a weight assigned thereto, wherein the weights increase from 0 to n-1, the circuit comprising:

• means responsive to a second binary number P including bits of weight 1 to n-2 of the first number X, for generating the square P.sup.2 of the second binary number, the means for generating including means for storing at least one bit of the P.sup.2 ;
• means for adding numbers, coupled to the means for generating, receiving at a first multi-bit input thereof, a number constituted by the bit of weight n-1 of the first number X and bits of the square P.sup.2 ;
• a first means for switching, coupled between the means for storing and the means for adding, receiving the second number P and providing the second number P to n-2 lines of low weight of a second input of the adder if a lowest weight bit of the first number X is equal to 1;
• a second means for switching, coupled between the means for storing and the means for adding, receiving the second number P and providing P to n-2 high weight lines of the second input of the adder if a bit of weight n-1 of the first number X is equal to 1;
• and
• a third means for switching, coupled between the means for storing and the means for adding, providing a l to a remaining line of the second input of the adder if bits of weight 0 and n-1 of the first number X are both equal to 1, wherein l represents a first predetermined logic level;
• wherein the square X.sup.2 of the first number X is provided by an output of the means for adding, and to the output of the means for adding are added at predetermined positions thereof a bit 0 and lowest weight bit of the first number X.

A squaring circuit comprising:

• a circuit responsive to a second binary number P, wherein each number P includes bits of weight 1 to n-2 of a binary number X to be squared, wherein binary number X has n bits, each bit having a weight assigned thereto, wherein the weights increase from 0 to n-1, the circuit for generating the square P.sup.2 of the second binary number and including a table stored in a membory having at least one bit of the P.sup.2 ;
• an adder, coupled to the circuit, receiving at a first multi-bit input thereof, a bit of weight n-1 of the first number X and bits of the square P.sup.2 of the second binary number;
• a first switching element, coupled between the memory and the adder, receiving the second number P and providing the second number P to n-2 lines of low weight of a second input of the adder if a lowest weight bit of the first number X is equal to 1, wherein l is a predetermined logic level;
• a second switching element, coupled between the memory and the adder, receiving the second number P and providing P to n-2 high weight lines of the second input of the adder if a bit of weight n-1 of the first number X is equal to 1;
• and
• a third switching element, coupled between the memory and the adder, providing 1 to a remaining line of the second input of the adder if bits of weight 0 and n-1 of the first number X are both equal to 1;
• wherein the square X.sup.2 of the first number X is provided by an output of the adder, and to the output of the adder are added at predetermined positions at bit 0 and lowest weight bit of the first number X.