Wide-band amplifier apparatus
AssigneeSony Corporation
InventorSeiichi Nishiyama
Life of this patent
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Abstract
In a wide-band amplifier circuit, a third and a fourth transistors are cascaded externally with a first and a second transistors within an integrated circuit which are connected each to output terminals by collectors through the output terminals, and a collector current flowing in the third transistor is transformed into an output voltage by an external resistance. A load capacity parasitic on the output terminal of the integrated circuit is driven by the collector current, thus a possibility of a frequency characteristic deteriorating due to an influence of the load capacity is avoided, and an operating zone can further be expanded to a high frequency band as compared with a prior art one.
Claims8
A wide-band amplifier circuit, comprising:
- differential amplification means constructed of a first and a second transistors, collectors being connected to a first and a second output terminals each, and driven by an input voltage supplied to bases;
- a third transistor provided externally of an integrated circuit with said differential amplification means mounted thereon, having the base connected to a direct current power terminal, and cascaded to said first transistor through said first output terminal;
- a fourth transistor connected to said third transistor, and also cascaded to said second transistor through said second output terminal;
- an external load resistance connected to a collector of said third transistor, and transforming a collector current supplied from said third transistor to said first transistor through said first output terminal into an output voltage;
- and
- a load capacity parasitic on said first output terminal being driven by said collector current.
A wide-band amplifier circuit, comprising:
- a differential input stage for inputting an input signal from a differential input end and outputting from a differential output and as an in-phase output signal and an anti-phase output signal;
- a first differential output stage for inputting said in-phase output signal and anti-phase output signal to first and second transistors, and outputting a first differential output from a first load resistance connected to a collector of the first or second transistor;
- a second differential output stage for inputting said in-phase output signal and anti-phase output signal to third and fourth transistors, and outputting a second differential output in-phase with said first differential output from a second load resistance connected to a collector of the third or fourth transistor;
- a first buffer transistor for supplying said first differential output to said second load resistance, and superposing the first differential output on said second differential output;
- a third differential output stage for inputting said in-phase output signal and anti-phase output signal to fifth and sixth transistors, and supplying an output current to an output end from the fifth or sixth transistor;
- and
- a second buffer transistor for supplying a combined output voltage of said first and second differential outputs which is anti-phase with said output current to the output end:
- wherein
- said output end being subjected to a push-pull drive.
Dependencies are inferred from the claim text.