Stable internal clock generation for an integrated circuit

Abstract

An integrated circuit, such as a microprocessor or math co-processor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input clock signal is disclosed. The clock generator circuit includes a programmable delay stage having fixed and variable portions. The fixed portion preferably includes a series of logic elements of various types (NOR, NAND, NOT, pass gates, etc.), selected to match the worst case clock phase delay and which match speed variations as a function of voltage, temperature or processing conditions. The variable portion of the delay stage selects a propagation delay by way of programmable elements (e.g., mask programmable); multiplexers may be included therein to allow selection of the delay in a test mode. The high frequency clock is generated by a circuit having a set input receiving the input clock signal and a reset input receiving the output of the programmable delay stage; as a result, the output clock signal duty cycle depends upon the propagation delay through the programmable delay stage, and not upon the duty cycle of the input clock signal. A frequency divider may also be provided to generate a lower frequency clock based on the input clock signal. In addition, the set and reset circuits may be disabled in a non-clock doubling mode, in which another frequency divider may be enabled for generating an output clock signal.

Dependencies are inferred from the claim text.