Frequency synthesizer with VCO output control

A frequency synthesis method, comprising the steps of:

• (a) generating, with a phase-locked-loop (PLL) means, a first control voltage for controlling a voltage-controlled oscillator (VCO) having a control input;
• (b) sampling with a control means, the first control voltage;
• (c) generating a second control signal for controlling the voltage-controlled oscillator, the second control signal being a sampled representation of the first control signal;
• (d) coupling the first control voltage to a capacitor which is coupled to the control input of the VCO during a phase-lock mode when the PLL means is phase locked;
• and
• (e) decoupling the first control voltage from the VCO, and coupling the second control voltage to the capacitor during a battery-saver mode when the power consumption of the PLL means is reduced in order to maintain a substantially constant control voltage at the control input of the VCO.

In a communication device including a voltage-controlled oscillator, a capacitor coupled to the voltage controlled oscillator, a phase-locked loop synthesizer means, an analog-to-digital converter, and digital-to-analog converter, a frequency synthesis method, comprising the steps of:

• (a) producing, with the phase-locked loop synthesizer means, a first control voltage, during a phase-lock mode where the PLL means is phase locked;
• (b) sampling the first control voltage using the analog-to-digital converter during the phase-lock mode;
• (c) storing a digitized version of the first control voltage sampled in step (b);
• (d) switching to a battery saver mode where the power consumption of the PLL means is reduced;
• and
• (e) producing a second control voltage using the digital-to-analog converter, during the battery saver mode, the second control voltage representing the digitized version of the first control voltage that was stored in step (c);
• (f) applying the second control voltage to the capacitor during battery-saver mode in order to maintain a substantially constant control voltage at the control input of the VCO.

In a communication device including a voltage-controlled oscillator, a capacitor coupled to the voltage controlled oscillator, a phase-locked loop synthesizer means, an analog-to-digital converter, and digital-to-analog converter, a frequency synthesis method, comprising the steps of:

• (a) producing, with the phase-locked loop synthesizer means, a first control voltage, during a phase-lock mode where the PLL means is phase locked;
• (b) sampling the first control voltage using the analog-to-digital converter during the phase-lock mode;
• (c) storing a digitized version of the first control voltage sampled in step (b);
• (d) switching to a battery saver mode where the power consumption of the PLL means is reduced;
• and
• (e) producing a second control voltage using the digital to analog converter, during the battery saver mode, the second control voltage representing the digitized version of the first control voltage that was stored in step (c),
• (f) applying the second control voltage to the capacitor during battery-saver mode in order to maintain a substantially constant control voltage at the control input of the VCO;
• (g) measuring a level of the second control voltage;
• (h) comparing the level of the second voltage with a digitized version of the first control voltage;
• (i) reprogramming the digital-to-analog converter to obtain an estimate of the first control voltage more accurate than the second control voltage, and powering down the analog-to-digital converter.