Microcomputer using specific instruction bit and mode switch signal for distinguishing and executing different groups of instructions in plural operating modes

A microcomputer comprising:

• instruction storing means for storing a common instruction group, a first operation mode instruction group, and a second operation mode instruction group, said groups including instructions of different kinds whose application operation modes are distinguished on the basis of a specific bit of an instruction and a mode switch signal;
• instruction register means for storing an instruction read from said instruction storing means;
• execution control means for controlling said storing operation of said instruction into said instruction register means, said execution control means outputting said mode switch signal;
• mode memory means for storing operation mode information indicative of one of a first and second operation mode of said application operation modes corresponding to a respective one of said first and second operation mode instruction groups in response to said mode switch signal given by said execution control means;
• first execution enable signal generating means for receiving the specific bit of the instruction from the instruction register means and the operation mode information from the mode memory means to generate a first execution enable signal when the operation mode information in said mode memory means indicates the first operation mode and when the specific bit of the instruction in said instruction register means is at a first value;
• second execution enable signal generating means for receiving the specific bit of the instruction from the instruction register means and the operation mode information from the mode memory means to generate a second execution enable signal when the operation mode information in said mode memory means indicates the second operation mode and when the specific bit of the instruction in said instruction register means is at a second value;
• first predecoder means for processing said instruction included in a first instruction group composed of the common instruction group, common to both said first and second operation modes and obtained when the specific bit of the instruction is at the first value, and the first operation mode instruction group obtained when the specific bit of the instruction is at the second value, said first predecoder means being operative in response to said first execution enable signal, said first predecoder means outputting first predecoded data;
• second predecoder means for processing said instruction included in a second instruction group composed of only the second operation mode instruction group obtained when the specific bit is at the second value, said second predecoder means being operative in response to said second execution enable signal, said second predecoder means outputting second predecoded data;
• programmable logic array means including a first unit for decoding said first predecoded data output from said first predecoder means and outputting a decoded result and a second unit for decoding said second predecoded data output from said second predecoder means and outputting a decoded result;
• and
• arithmetic logic means, coupled to said programmable logic array means, for performing an arithmetic operation on the decoded result from said programmable logic array means.