US 5,335,327 AGranted

External memory control techniques with multiprocessors improving the throughput of data between a hierarchically upper processing unit and an external memory with efficient use of a cache memory

AssigneeHitachi, Ltd.

InventorsKiyoshi Hisano, Ken Hirashima, Hiroyuki Kurosawa, Kenji Kubota, Shuji Sugimoto

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Abstract

A disk unit control apparatus (DKC) comprises a cache memory provided between a CPU and an external memory (DKU) storing the information exchanged with the CPU, the cache memory holding temporarily copies of the information stored in the DKU. A request from the CPU for access to the information stored in the DKU is met as far as possible by use of the information held in the cache memory. First transfer routes of information between the CPU and the cache memory is greater in number than second transfer routes of information between the cache memory and the DKU. This makes it possible that even when direct accesses to the DKU in the same number as the second transfer routes occur in each of the first transfer route, accesses to the cache memory which may arise from other CPUs are capable of being effected through the remaining ones of the first transfer routes. As a result, a cache memory accessible with high speed is obtained, and the utilization efficiency of the data stored in the cache memory is substantially improved, improving the data throughput between the CPU and the DKU.

Claims9

Dependent claims

A control apparatus interposed between a hierarchically upper processing unit and an external memory device, comprising:

a channel switch circuit connected to a plurality of channels from the upper processing unit for accepting an access request from the channels;
a plurality of channel ports selected by the channel switch circuit;
a cache memory interposed between the upper processing unit and the external memory device for storing information exchanged with the upper processing unit, said cache memory including means for temporarily holding copies of the information stored in the external memory device;
a plurality of information paths for selectively communicating among the upper processing unit, the cache memory and the external memory device, the plurality of information paths comprising:
first path means for establishing a first information exchange path between the cache memory and each of the plurality of channel ports,
second path means for establishing a second information exchange path between the external memory device and each of the plurality of channel ports;
a plurality of first control processors provided for the plurality of channel ports respectively for detecting conditions of the cache memory in response to the access request from a one of the plurality of channels and for independently controlling selection of the first and second information exchange paths by the channel ports;
a plurality of third path means for establishing a third information exchange path between the cache memory and the external memory device, a number of the third path means being smaller than a total number of the first path means;
a plurality of second control processors provided for the third path means respectively for selectively establishing the second and third information exchange paths to the external memory device, wherein the plurality of second control processors is smaller in number than the plurality of first control processors;
and
processor supervisor means for establishing communications between the first and second control processors, for establishing independent operation of each of the control processors and controlling competition between the control processors, in such a manner that the access request from the channels for accessing the external memory device is applied to the cache memory as far as possible to effect reading and writing of requested information between the cache memory and the upper processing unit.

8 more elements

A method for controlling a data transfer between a hierarchically upper processing unit and an external memory device, wherein a means for switching data between the upper processing unit and the external memory device includes:

a cache memory;
a plurality of first data transfer routes for selectively connecting a plurality of channel ports to the cache memory;
a plurality of third data transfer routes for selectively connecting the plurality of interfaces from the external memory device to the cache memory, wherein the first data transfer routes are greater in number than the third data transfer routes;
a plurality of first control processors provided for the plurality of channel ports respectively for detecting conditions of the cache memory in response to an access request from the upper processing unit and for independently controlling a selection of the first and second data transfer routes by the channel ports;
a plurality of second control processors provided for the plurality of interfaces respectively for independently and selectively connecting the second and third data transfer routes to the external memory device;
the plurality of first control processors being greater in number than the plurality of second control processors;
processor supervisor means for establishing communications between the first and second control processors, for establishing independent operation of each control processors and controlling competition between the control processors;
and,
the method comprising the steps of:
requesting a first target data by the upper processing unit from the external memory device,
determining if the first target data is stored in the cache memory,
for a cache hit, transferring the first target data from the cache memory to a first usable channel port of the plurality of channel ports by a one of the first data transfer routes, and
for a cache miss, transferring the first target data from the external memory device to the first usable channel port by a first one of the plurality of second data transfer routes, wherein the first data transfer routes operate independently from and in parallel with the transferring by the second data transfer routes.

10 more elements

Dependencies are inferred from the claim text.