US 5,335,321 AGranted

Scalable multimedia platform architecture

AssigneeIntel Corporation

InventorsKevin Harney, Louis A. Lippincott

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Abstract

The scalable platform architecture of the present video processing system invention includes a bus for transmitting data between various video processing subsystems. A graphics processing subsystem is coupled to the bus. A central processing unit is coupled to the bus and performs video processing. The graphics processing subsystem is adapted to receive a video memory and to perform video processing when the video memory is received. The bus is provided with expansion connectors for detachably coupling to a video processing subsystem and a video capture system. The addition of the video processing subsystem and/or video capture subsystem accelerates the processing of the video processing system by performing video processing that would otherwise be performed by the central processing unit.

Claims4

Dependent claims

A video processing system comprising:

bus means for transmitting data;
graphics processing means coupled to said bus means for performing graphics processing;
a central processing unit coupled to said bus means and for performing video processing;
first connecting means for detachably receiving a video acceleration subsystem for performing video processing and electrically coupling said bus means to said video acceleration subsystem, wherein said video acceleration subsystem accelerates said video processing system by performing at least some of the video processing otherwise performed by said central processing unit;
and
second connecting means for detachably receiving a video capture subsystem for performing video capture processing and for electrically coupling said bus means to said video capture subsystem, wherein said video capture subsystem accelerates said video processing system by performing video capture processing otherwise performed by said central processing unit.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 07/901,383Filed 19 Jun 1992
Granted: 2 Aug 1994
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G09G 5/363
Characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory: graphics controllers
G06F 3/14
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for…: digital…
G06F 13/423
Being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus: with synchronous protocol
G09G
Arrangements or circuits for control of indicating devices using static means to