System and method for scaling a digital image

An image scaling circuit for scaling the size of a first digital image to generate a second digital image by a desired scaling factor, the image scaling circuit comprising:

• interpolator means for magnifying the first digital image by a first scaling factor greater than or equal to one, and for generating a corresponding intermediate digital image having a first plurality of pixels;
• said first scaling factor determined by the desired scaling factor and a second scaling factor;
• shrinking means, coupled to said interpolator means, for shrinking said intermediate digital image generated by said interpolator means by said second scaling factor, wherein said second scaling factor is limited to always be a power of two to thereby generate the second digital image, said second digital image containing a second plurality of pixels, each one of said second plurality of pixels corresponding to a quantity of said first plurality of pixels, wherein said corresponding quantity of said first plurality of pixels is a power of two, and further for averaging said pixel values of each of said corresponding quantity of said first plurality of pixels, and further for assigning said average value to said pixel value of said corresponding one of said second plurality of pixels corresponding to said quantity of said first plurality of pixels, said second scaling factor thereby reducing said intermediate digital image by a power of two;
• and
• controller means, coupled to said interpolator means and said shrinking means, for controlling the operation of the apparatus,
• wherein said first scaling factor is determined based upon the desired scaling factor and said second scaling factor.

A method for scaling a first digital image by a desired scaling factor to a second digital image in an image processor comprising an interpolator having an input and an output, and a shrinking logic circuit having an input coupled to the output of the interpolator, the interpolator and the shrinking logic circuit coupled to and controlled by a controller means, the image processor further comprising a first buffer means coupled to the input of the interpolator and coupled to and controlled by the controller means, and a second buffer means coupled to the output of the shrinking logic circuit and coupled to and controlled by the controller means, the method comprising the steps of:

• (a) receiving the first digital image from an external source by said first buffer means and to store the first digital image in said first buffer means;
• (b) said controller means sending a first instruction to said first buffer means to provide the first digital image stored in said first buffer means to said interpolator;
• (c) said controller means sending a second instruction signal to said interpolator to initiate a first scaling operation which comprises the steps of:
• (i) receiving the first image by said interpolator, and
• (ii) enlarging the first image by a first scaling factor greater than or equal to one by said interpolator to result in an enlarged image having a first plurality of pixels, said first scaling factor determined by the desired scaling factor and a second scaling factor which is limited to always be a power of two;
• (d) controller means sending a third instruction signal to said shrinking logic circuit to initiate a second scaling operation which comprises the steps of:
• (i) receiving said enlarged image from said interpolator by said shrinking logic circuit, and
• (ii) reducing said enlarged image received from said interpolator by said second scaling factor to produce the second digital image by said shrinking logic circuit, said second digital image comprising a second plurality of pixels, each one of said second plurality of pixels corresponding to a quantity of said first plurality of pixels, wherein said corresponding quantity of said first plurality Of pixels is a power of two, said reducing step comprising the steps of:
• (1) dividing said enlarged image into a plurality of cells, each of said plurality of cells including a power of two quantity of said first plurality of pixels,
• (2) adding the values of each of said quantity of said first plurality of pixels, resulting in a total pixel value for each of the plurality of cells, and
• (3) averaging said total pixel value for each of said corresponding quantity of said first plurality of pixels;
• (e) said controller means sending a fourth instruction signal to said shrinking logic circuit to provide the second digital image to said second buffer means;
• and
• (f) said controller means sending a fifth instruction signal to said second buffer means to receive the second digital image from said shrinking logic circuit and to store the second digital image in said second buffer means.