Error correction code pipeline for interleaved memory system

A digital computer system having all error correcting data pipeline between an interleaved storage device having first and second memory banks and a receiving device, the pipeline comprising:

• (a ) an input latch mechanism, electrically connected to said first and second memory banks, for alternately transmitting first and second portions of data received from said first and second memory banks of said storage device:
• b) all output latch mechanism, electrically connected to said receiving device, for alternately transmitting first and second portions of corrected data to said receiving device;
• (c) error correcting circuitry (ECC) connected between said input and output latch mechanisms for alternately receiving said first and second portions of said data from said input latch mechanism, correcting errors in said data and sending said first and second portions of said corrected data to said output latch mechanism;
• and
• (d) a control signal electrically corrected to said input latch mechanism, said output latch mechanism, and said error correcting circuitry for simultaneously latching 1) one of said first and second portions of said data from said first and second memory banks to said input latch mechanism, 2) one of said first and second portions of said data from said input latch mechanism to said error correcting circuitry, 3) one of said first and second portions of said corrected data to said output latch mechanism;
• (e) wherein said data from said interleaved storage device is alternately latched into said input latch mechanism for error correction, and alternately provided from said error correcting circuitry to said output latch mechanism as corrected data.