Semiconductor integrated circuit device

Abstract

A semiconductor IC device includes a memory cell group; a pair of bit lines connected to the cell group; plural equalization transistors T.sub.R connected between the bit lines; address transition detectors ATD for detecting changes in address bits; and plural equalizing pulse generating circuits composed of plural logical gates, 15 to 22, respectively and provided for each equalization transistor to generate an equalizing pulse signal to each equalization transistor so that the levels of the two bit lines can be equalized with each other. Since signals outputted from the address transition detectors are synthesized, in particular at a node to which the equalizing pulse signal is applied, the number of logical gate stages to synthesize the detector output signals can be reduced and the wire lengths (e.g. wire capacitances) of the logical gates can be well balanced, thus improving the equalizing speed of the IC device.

Dependencies are inferred from the claim text.