US 5,335,205 A · DRAM using word line potential control circuitcircuit

Abstract

Memory, cells includes at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS transistor for transferring a potential to the word line. The word line drive circuit is controlled by an output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.

Claims22

Dependent claims

A semiconductor memory device, comprising:

memory cells connected to word lines, at least one of said memory cells including a MOS transfer gate transistor of a first conductivity type having a threshold voltage Vth;
word line drive means for driving said word lines during a word line selection mode;
and
word line potential control means for outputting at an output terminal thereof a word line drive signal to said word line drive means, said word line drive signal having, if said MOS transfer gate transistor of the first conductivity type is an N-channel MOS transistor, a first level which is not higher than a first power source potential Vcc and not lower than the threshold voltage Vth and a second level which is higher than said first power source potential Vcc, and said word line drive signal having, if said MOS transfer gate transistor of the first conductivity type is a P-channel MOS transistor, a first level which is not lower than a second power source potential Vss and not higher than the threshold voltage Vth and a second level which is lower than said second power source potential Vss.

1 more element

A semiconductor memory device, comprising:

memory cells coupled to word lines, at least one of said memory cells including a MOS transistor of a first conductivity type having a threshold voltage Vth, and a MOS capacitor;
word line drive means for driving said word lines during a word line selection mode;
and
word line potential control means for outputting at an output terminal thereof a word line drive signal to said word line drive means, said word line drive signal having, if said MOS transistor of the first conductivity type is an N-channel MOS transistor, a first level which is not higher than a first power source potential Vcc and not lower than the threshold voltage Vth and a second level which is higher than said first power source potential Vcc, and said word line drive signal having, if said MOS transistor of the first conductivity type is a P-channel MOS transistor, a first level which is not lower than a second power source potential Vss and not higher than the threshold voltage Vth and a second level which is lower than said second power source potential Vss.

1 more element

A semiconductor memory device comprising:

memory cells connected to word lines and bit lines;
rod line driving circuitry coupled to said word lines for driving said word lines during a word line selection mode;
and
word line potential control circuitry coupled to said word line driving circuitry for supplying a word line driving signal to said word line driving circuitry, said word line driving signal having a first level whenever said semiconductor memory device is not in said word line selection mode and said word line driving signal having a second level different than the first level whenever said semiconductor memory device is in said word line selection mode,
wherein said word line potential control circuitry includes,
an input terminal receiving a signal for setting said word line selection mode;
an inverter having an input coupled to said input terminal;
a first capacitor having a first terminal coupled to said input terminal;
a second capacitor having a first terminal coupled to an output of said inverter;
a first MOS transistor of a first conductivity type having a gate coupled to a first power source potential, a first terminal coupled to a second terminal of said first capacitor, and a second terminal coupled to said first power source potential;
a second MOS transistor of the first conductivity type having a gate coupled to a node between said first terminal of said first MOS transistor and said second terminal of said first capacitor, a first terminal coupled to a second terminal of said second capacitor, and a second terminal coupled to said first power source potential;
a third MOS transistor of the first conductivity type having a gate coupled to said first power source potential, a first terminal coupled to said first power source potential, and a second terminal coupled to a node between said first terminal of said second MOS transistor and said second terminal of said second capacitor;
and
an output terminal coupled to said second terminal of said third MOS transistor.

11 more elements

A semiconductor memory device comprising:

memory cells connected to word lines and bit lines;
word line driving circuitry coupled to said word lines for driving said word lines during a word line selection mode;
and
word line potential control circuitry coupled to said word line driving circuitry for supplying a word line driving signal to said word line driving circuitry, said word line driving signal having a first level whenever said semiconductor memory device is not in said word line selection mode and said word line driving signal having a second level different than the first level whenever said semiconductor memory device is in said word line selection mode, wherein said memory cells are arranged in a plurality of memory cell blocks and said word line potential control circuitry includes a block activation circuit for outputting said word line driving signal to a selected memory cell block, said block activation circuit including
a first input terminal receiving said word line driving signal;
a second input terminal for receiving a first address signal;
a first MOS transistor of a first conductivity type having a control gate coupled to a first power source potential and a first terminal coupled to said second input terminal;
a second MOS transistor of the first conductivity type having a gate applied with said first address signal and a first terminal coupled to a second power source potential;
a third MOS transistor of a second conductivity type having a control gate coupled to a second terminal of said first MOS transistor, a first terminal coupled to said first input terminal, a second terminal coupled to a second terminal of said second MOS transistor, and a back gate coupled to said first input terminal;
a fourth MOS transistor of the second conductivity type having a control gate coupled to a node between said second terminal of said second MOS transistor and said second terminal of said third MOS transistor, a first terminal coupled to said second terminal of said first MOS transistor, a second terminal coupled to said first input terminal, and a back gate coupled to said first input terminal;
a fifth MOS transistor of the second conductivity type having a control gate coupled to said second terminal of said first MOS transistor, a first terminal coupled to said first power source potential, and a back gate coupled to said first input terminal;
a sixth MOS transistor having a control gate coupled to said node between said second terminal of said second MOS transistor and said second terminal of said third MOS transistor, a first terminal coupled to said first input terminal, a second terminal coupled to a second terminal of said fifth MOS transistor, and a back gate coupled to said first input terminal;
an inverter having an input receiving said first address signals;
a first output terminal coupled to an output of said inverter;
and
a second output terminal coupled to anode between said second terminal of said fifth transistor and said second terminal of said sixth transistor for outputting said word line driving signal.

13 more elements

A semiconductor memory device comprising:

memory cells connected to word lines and bit lines;
word line driving circuitry coupled to said word lines for driving said word lines during a word line selection mode;
and
word line potential control circuitry coupled to said word line driving circuitry for supplying a word line driving signal to said word line driving circuitry, said word line driving signal having a first level whenever said semiconductor memory device is not in said word line selection mode and said word line driving signal having a second level different than the first level whenever said semiconductor memory device is in said word line selection mode,
wherein said word line potential control circuitry includes,
an input terminal receiving a signal for setting said word line selection mode;
a first inverter having an input connected to said input terminal;
a capacitor having a first terminal coupled to an output of said first inverter;
a depletion-type first MOS transistor of a first conductivity type having a control gate coupled to said input terminal, a first terminal coupled to a second terminal of said capacitor, and a second terminal coupled to a first power source potential;
and
an output terminal coupled to said second terminal of said capacitor for outputting the word line driving signal to a selected block.

8 more elements

Dependencies are inferred from the claim text.

DRAM using word line potential control circuitcircuit

Life of this patent

DRAM using word line potential control circuitcircuit

Life of this patent

Abstract

Claims22