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US 5,335,204 AGranted
Semiconductor integrated circuit device
AssigneesHitachi, Ltd., Hitachi VLSI Engineering Corp.
InventorsAkinori Matsuo, Masashi Watanabe, Michio Fujimoto, Masashi Wada, Yoshiharu Nagayama, Kazuo Naito
Life of this patent
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Abstract
Means for changing-over address signals is provided in an address input portion, and the order of the signals to be input to an address decoder is changed according to external control signals. Alternatively, a reading output circuit is provided which reads data in bit unit different from that of the writing input circuit. Thus, data can be read and written even when the number of bits of data differs between in case of accessing a built-in memory of an LSI inside the LSI and in case of accessing it from outside the LSI.
Claims20
A semiconductor integrated circuit device comprising:
- external terminals;
- a plurality of word lines;
- a plurality of data lines;
- a plurality of memory cells coupled to the plurality of word and data lines so that each memory cell is coupled to one word line and to one data line;
- word line selection means for selecting one of the plurality of word lines;
- first common data lines;
- first selection means for selectively coupling selected ones of the plurality of data lines to the first common data lines, respectively;
- second common data lines, a number of which is smaller than that of the first common data lines;
- second selection means for selectively coupling selected ones of the first common data lines to the second common data lines so that the selected ones of the plurality of data lines are coupled to the second common data lines via the selected ones of first common data lines;
- read-out means coupled to the first common data lines and for selectively providing first data based on read-out data appearing on the first common data lines when the read-out means is brought into an operation state in response to a first control signal;
- input and output means coupled between the external terminals and the second common data lines for selectively inputting externally generated data received at the external terminals to the memory cells or outputting second data based on read-out data appearing on the second common data lines to the external terminals when the input and output means is brought into an operation state in response to a second control signal;
- and
- circuit means coupled to the read-out means and for selectively receiving the first data.
10 more elements
A semiconductor integrated circuit device comprising:
- external terminals;
- a plurality of word lines;
- a plurality of first data lines;
- a plurality of memory cells coupled to the plurality of word lines and first data lines so that each memory cell is coupled to one word line and to one first data line;
- a word line selection circuit for selecting one of the plurality of word lines;
- common data lines;
- a first selection circuit for selectively coupling selected ones of the plurality of first data lines to the common data lines, respectively;
- second data lines, a number of which is smaller than that of the common data lines;
- a second selection circuit for selectively coupling selected ones of the common data lines to the second data lines in a first mode so that the selected ones of the plurality of first data lines are coupled to the second data lines via the selected ones of the common data lines;
- a read-out circuit coupled to the common data lines and for selectively providing first data based on read-out data appearing on the common data lines in a second mode;
- an input circuit coupled between the external terminals and the second data lines for selectively inputting second data based on externally generated data received at the external terminals to the memory cells in the first mode;
- and,
- circuit means coupled to the read-out means and for selectively receiving the first data.
10 more elements
A semiconductor integrated circuit device comprising:
- external terminals;
- a plurality of word lines;
- a plurality of first data lines;
- a plurality of memory cells coupled to the plurality of word lines and first data lines so that each memory cell is coupled to one word line and to one first data line;
- a word line selection circuit for selecting one of the plurality of word lines;
- common data lines;
- a first selection circuit for selectively coupling selected ones of the plurality of first data lines to the common data lines, respectively;
- second data lines, a number of which is smaller than that of the common data lines;
- a second selection circuit for selectively coupling selected ones of the common data lines to the second data lines in a first mode so that the selected ones of the plurality of first data lines are coupled to the second data lines via the selected ones of the common data lines;
- a read-out circuit coupled to the common data lines and for selectively providing first data based on read-out data appearing on the common data lines in a second mode;
- an output circuit coupled between the external terminals and the second data lines for selectively outputting second data based on read-out data appearing on the second data lines to the external terminals in the first mode;
- and,
- circuit means coupled to the read-out means and for selectively receiving the first data.
10 more elements
Dependencies are inferred from the claim text.