Method for providing synchronous refresh cycles in self-refreshing interruptable DRAMs

A method for refreshing a plurality of memory devices, each memory device having a refresh circuit, a timing circuit, at least one internal control device, and an external refresh pin, said refresh pins of said plurality of memory devices connected at a common node, said refresh pins for alternately receiving a first and a second potential, said first and second potentials having substantially different voltage levels, comprising the following steps:

• a) initiating a timing sequence in said timing circuits of said plurality of memory devices to provide an active timing signal at a timing circuit output terminal in at least one of said memory devices;
• b) activating at least one of said internal control devices in response to said active timing signal to pull said refresh pins of said plurality of memory devices to said second potential;
• c) resetting said timing circuits of said plurality of memory devices in response to said second potential on said refresh pins;
• and
• d) providing a refresh signal in response to said second potential on said refresh pins to initiate synchronous refresh cycles in said refresh circuits of said plurality of memory devices;
• and
• e) refreshing said plurality of memory devices during said synchronous refresh cycles.

A method for operating a memory system, comprising the following steps:

• a) providing bi-directional electrical communication, at a common node, between a plurality of memory devices;
• b) generating a refresh message at said common node, said step of generating performed by one of said memory devices of said plurality;
• and
• c) synchronously refreshing said memory devices of said plurality in response to said refresh message, said synchronously refreshing performed by an internal refresh circuit of at least one of said memory devices.

A method of operating a bank of memory devices, comprising the following steps:

• a) providing electrical interaction between all of the memory devices of the bank;
• b) generating a refresh signal in one memory device of the bank;
• c) communicating said refresh signal to said memory device performing said step of generating;
• d) communicating said refresh signal to remaining memory devices of the bank;
• and
• e) synchronously refreshing all of the memory devices in the bank in response to said refresh signal.

A method of operating a memory system, comprising the following steps:

• a) activating an internal refresh circuit of a first memory device;
• b) refreshing said first memory device with said internal refresh circuit;
• c) providing an electrical interaction between said first memory device and a second memory device;
• and
• d) refreshing said second memory device in response to said internal refresh circuit;
• and wherein said step so refreshing said first and second memory devices are performed synchronously.

A method for refreshing a plurality of self-refreshing DRAMs, comprising the following steps:

• a) pulling an external refresh pin of each of the self-refreshing DRAMs of the plurality to a first potential prior to performing the refreshing;
• b) generating an active timing circuit output signal in one of the self-refreshing DRAMs of the plurality;
• c) driving said external refresh pin of the self-refreshing DRAM having said active timing circuit output signal to a second potential in response to said active timing circuit output signal;
• d) driving all of said external refresh pins of the self-refreshing DRAMs of the plurality to said second potential in response to said second potential on said external refresh pin of the self-refreshing DRAM having said active timing circuit output signal;
• and
• e) synchronously refreshing a row of memory cells in each of said self-refreshing DRAMs of said plurality in response to said second potential on said external refresh pins, said step of synchronously refreshing performed by at least one refresh circuit in at least one of said self-refreshing DRAMs of said plurality.

A method for refreshing a bank of self-refreshing DRAMs, comprising the following steps:

• a) generating an active refresh signal in one of the self-refreshing DRAMs of the bank;
• b) communicating said active refresh signal from said one of the self-refreshing DRAMs of the bank to remaining said self-refreshing DRAMs of the bank;
• p1 c) synchronously refreshing a row of memory storage cells in each of the self-refreshing DRAMs of the bank in response to said refresh signal, said step of synchronously refreshing performed by at least one refresh circuit in at least one of said self-refreshing DRAMs of said bank;
• and
• d) interrupting a microprocessor during said step of refreshing.

A method for refreshing a bank of DRAMs comprising the following steps:

• a) generating an active reset signal at an external node, said active reset signal generated in one of said DRAMs of said bank;
• b) communicating said reset signal to all of said DRAMs in said bank;
• c) resetting a timing circuit in each of said DRAMs in said bank in response to said active reset signal;
• d) generating a refresh signal in each of said timing circuits;
• e) activating a refresh circuit in each of said DRAMs of said bank in response to said refresh signal;
• and
• f) synchronously refreshing each of said DRAMs of said bank with an activated said refresh circuit.

A method for reducing wait states and increasing microprocessor speed in a memory device comprising a plurality of self-refreshing DRAMs, comprising the following steps:

• a) initializing a timing sequence in each of the self-refreshing DRAMs of the plurality;
• b) generating a reset signal in one of said self-refreshing DRAMs of said plurality at a conclusion of at least one of said timing sequences;
• c) synchronously refreshing all of the self-refreshing DRAMs of the plurality in response to said reset signal;
• and
• d) initiating a wait state in said microprocessor during said step of synchronously refreshing.