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US 5,335,199 AGranted
Multiport memory
AssigneeFujitsu Limited
InventorKeizo Aoyama
Life of this patent
Estimating the term…
Abstract
A multiport memory that allows simultaneous reading and/or writing to the same memory cells by shorting selected bit lines with other bit lines of cells whose row address from each port match.
Claims33
A multiport memory, comprising:
- static memory cells;
- ports provided for writing or reading data to or from said static memory cells;
- independent bit lines and word lines with levels and corresponding to said ports;
- switches adapted to electrically connect said bit lines, corresponding to said word lines of a same port, to said static memory cells depending on the levels of said word lines;
- and
- short-circuit devices adapted to substantially short-circuit between the bit lines of each column of corresponding ports at a time a same row is selected by the corresponding ports.
3 more elements
A multiport memory, comprising:
- static memory cells;
- ports provided for write or read operations to or from said static memory cells;
- independent bit lines and word lines with signal levels and corresponding to said ports;
- switches adapted to electrically connect said bit lines, corresponding to said word lines of a same port, to said static memory cells depending on the signal levels of said word lines;
- and
- short-circuit devices adapted to substantially short circuit between the bit lines corresponding to the port selected for a write operation among the bit lines corresponding to a plurality of selected ports and other bit lines when word lines belonging to a same row are selected from the plurality of the ports for the write or read operation, said short-circuit devices comprising:
- a row address matching detection circuit which compares row addresses input to respective ports with each other and outputs a signal when the row addresses of the ports match;
- and
- a short-circuit switch connected to said detection circuit and the row bit lines and which receives the output signal from said row address matching detection circuit and short-circuits the bit lines of each column of corresponding ports.
6 more elements
A multiport memory, comprising:
- static memory cells;
- a first port and a second port provided for a write or a read operation to or from said static memory cells;
- independent first and second bit lines and independent first and second word lines having levels and provided corresponding to said first and second ports;
- switches adapted to electrically connect said bit lines corresponding to said first and second word lines of a same port to said static memory cells depending on the levels of said first and second word lines;
- and
- short-circuit devices adapted to substantially short circuit between the bit lines of each column of said first and second corresponding ports at a time a same row is selected by said first and second ports.
3 more elements
A multiport memory, comprising:
- static memory cells;
- a first port and a second port provided for a write or a read operation to or from said static memory cells;
- independent first and second bit lines and independent first and second word lines having levels and provided corresponding to said first and second ports;
- switches for electrically connecting said bit lines corresponding to said first and second word lines of a same port to said static memory cells depending on cells of said first and second word lines;
- and
- short-circuit devices for substantially short-circuiting between the bit lines of each column of corresponding ports at a time a same row is selected by a plurality of said ports, said short-circuit devices comprising:
- a row address matching detection circuit which compares row addresses input to respective ports with each other and outputs a signal when the row addresses of the plurality of ports match;
- and
- a short-circuit switch connected to the detection circuit and to the row bit lines and which receives the signal from said row address matching detection circuit and substantially short circuits the bit lines of each column of corresponding ports.
6 more elements
A multiport memory, comprising:
- static memory cells;
- a first port and a second port provided for a write or a read operation to or from said static memory cells;
- first and second bit lines and first and second word lines having levels and provided corresponding to said first and second ports;
- switches for electrically connecting said bit lines corresponding to said first and second word lines of a same port to said static memory cells depending on the levels of said first and second word lines;
- and
- short-circuit devices for substantially short-circuiting the bit lines corresponding to the ports selected for the write operation and other selected bit lines among the first and second bit lines, when the first and second word lines belonging to a same row are selected from the read or the write operation;
- a row address matching detection circuit which compares row addresses input to respective ports with each other and outputs a signal when the row addresses of the ports including those selected for the write operation match;
- a first cell region and a second cell region which may be formed by dividing said word lines in a cell region of said static memory cells into two regions;
- a right row decoder provided between said first cell region and said second cell region, corresponding to a right port;
- and
- a left row decoder provided between said first cell region and said second cell region, corresponding to a left port;
- and
- said short-circuit devices receive an output of said row address matching detection circuit and generate a short-circuit of the bit lines corresponding to the ports selected for the write operation and other selected bit lines, among the bit lines corresponding to the respective ports.
10 more elements
A multiport memory, comprising:
- static memory cells arranged in an array of rows and columns and having at least two independent bit lines corresponding to at least two ports providing cell addresses;
- and
- a short circuit device coupled to the independent bit lines and to receive the cell addresses and short circuit connecting between the bit lines of corresponding columns at a time that the cell addresses match.
Dependencies are inferred from the claim text.