Flash EEPROM array with high endurance
AssigneeAdvanced Micro Devices, Inc.
InventorsMichael A. Van Buskirk, Kevin W. Plouse, Joseph G. Pawletko, Chi Chang, Sameer S. Haddad, Ravi P. Gutala
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Abstract
An over-erased bit correction structure is provided for performing a correction operation on over-erased memory cells in an array of flash EEPROM memory cells during programming operations so as to render high endurance. Sensing circuitry (23) is used to detect column leakage current indicative of an over-erased bit. If an over-erased bit is determined, a pulse counter (25) is activated so as to apply programming pulses to the control gate of the selected memory cell so as to program back the negative threshold voltage of the over-erased bit to a positive voltage.
Claims18
In a semiconductor integrated memory device having an over-erased bit correction structure for performing a correction operation on over-erased memory cells in the memory device, said correction structure comprising in combination:
- a cell matrix (12) having a plurality of memory cells (MC) arrayed in rows of word lines and columns of bit lines intersecting said rows of word lines, each of said memory cells including a floating gate array transistor having its control gate connected to one of said rows of word lines, its drain connected to one of said columns of bit lines, and its source connected to a ground potential;
- row decoder means (14) responsive to row address signals and being operatively connected to said cell matrix for selecting one of said rows of word lines;
- column decoder means (18) responsive to column address signals and being operatively connected to said cell matrix for selecting one of said columns of bit lines;
- reference column means (116) including a plurality of reference cells (RC) arrayed in rows of word lines corresponding to the number of rows in said cell matrix, each of said reference cells including a reference cell transistor (Q.sub.R) having its gate connected to the same one of said rows of word lines, its drain connected to a reference bit line, and its source connected to the ground potential;
- sensing circuit means (23) for comparing leakage current in the selected one of said columns of bit lines and a reference current in the reference column means during a program verify mode of operation and for generating a logic signal which is at a high logic level when said bit line leakage current is greater than said reference current indicative of an over-erased memory cell and which is at a low logic level when said bit line leakage current is less than said reference current indicative of a properly programmed memory cell;
- and
- pulse counter means (25) coupled to said row decoder means for providing a plurality of programming pulses one at a time to the selected one of said rows of word liens and to the control gate of the array transistor in a first selected memory cell to be programmed during programming of the first selected memory cell in the selected one of said columns of bit lines until said logic signal generated by said sensing circuit means is at the low logic level so as to program back simultaneously all over-erased memory cells connected to the same selected one of said columns of bit lines.
An over-erased bit correction structure for correcting over-erased memory cells in an array of flash EEPROM memory cells during program operation so as to render high endurance, said correction structure comprising:
- a cell matrix (12) having a plurality of memory cells (MC) arrayed in rows of word lines and columns of bit lines intersecting said rows of word lines, each of said memory cells including a floating gate array transistor having its control gate connected to one of said rows of word lines, its drain connected to one of said columns of bit lines, and its source connected to a ground potential;
- row decoder means (14) responsive to row address signals and being operatively connected to said cell matrix for selecting one of said rows of word lines;
- column decoder means (18) responsive to column address signals and being operatively connected to said cell matrix for selecting one of said columns of bit lines;
- reference column means (116) including a reference cell transistor (Q.sub.R);
- sensing circuit means (23) for comparing leakage current in the selected one of said columns of bit lines and a reference current in the reference column means during a program verify mode of operation and for generating a logic signal which is at a high logic level when said bit line leakage current is greater than said reference current indicative of an over-erased memory cell and which is at a low logic level when said bit line leakage current is less than said reference current indicative of a properly programmed memory cell;
- and
- pulse counter means (25) coupled to said row decoder means for providing a plurality of programming pulses one at a time to the selected one of said rows of word lines and to the control gate of the array transistor in a first selected memory cell to be programmed during programming of the first selected memory cell in the selected one of said columns of bit lines until said logic signal generated by said sensing circuit means is at the low logic level so as to program back simultaneously all over-erased memory cells connected to the same selected one of said columns of bit lines.
Dependencies are inferred from the claim text.