High dielectric constant capacitor and method of manufacture

A high dielectric constant stacked storage capacitor for a semiconductor structure, comprising:

• a polysilicon electrode formed in an electrically insulating layer of the semiconductor structure;
• a barrier layer formed of an electrically conductive material deposited on the polysilicon electrode;
• a lower electrode of a non-oxidizing electrically conductive material deposited on the barrier layer and etched to provide a plurality of stacked structures with gaps therebetween each stacked structure having sidewalls;
• spacers formed of a material different than the conductive material for the lower electrode deposited in the gaps and on the sidewalls to protect the barrier layer from oxidation and having a planarized surface formed by chemical mechanical planarization (CMP) to an endpoint of the lower electrode to provide a smooth and planar surface for deposition of a dielectric layer;
• a dielectric layer formed of a high dielectric constant material deposited on the smooth surface of the lower electrode and spacers;
• and
• and upper electrode of a conductive material formed on the dielectric layer.

A method of forming a high dielectric constant capacitor comprising the steps of:

• forming an electrically insulating layer on a semiconductor transistor structure;
• forming a polysilicon electrode in the insulating layer to a silicon electrode layer of the transistor structure;
• forming a barrier layer by depositing an electrically conductive material on the polysilicon electrode;
• forming a lower electrode by depositing a non-oxidizing electrically conductive material on the barrier layer and etching said non-oxidizing conductive material along with said barrier layer to form an array of stacked structures having sidewalls and gaps therebetween;
• depositing a material different than the lower electrode into the gaps and onto the sidewalls and etching said different material to form spacers to protect the barrier layer from oxidation said spacers having a contoured surface to provide an increased surface area and a smooth topography for deposition of a dielectric layer;
• depositing a high dielectric constant film over the smooth topography provided by the lower electrode and spacers;
• and
• depositing an electrically conductive material on the high dielectric constant film to form an upper electrode.

A method of forming a high dielectric constant capacitor comprising the steps of:

• forming an electrically insulating layer on a semiconductor transistor structure;
• forming a polysilicon electrode in the insulating layer to a silicon electrode layer of the transistor structure;
• forming a lower electrode by depositing a non-oxidizing electrically conductive material on the barrier layer and etching said non-oxidizing conductive material along with said barrier layer to form an array of stacked structures having sidewalls and gaps therebetween;
• depositing a material different than the lower electrode to cover the sidewalls and completely fill the gaps and chemically mechanically planarizing said different material to an endpoint of said lower electrode to provide a planar topography for deposition of a dielectric layer and to provide protection for the sidewalls;
• depositing a high dielectric constant film over the planar topography provided by the lower electrode and spacers;
• and
• depositing a conductive material on the high dielectric constant film to form an upper electrode.