US 5,335,105 A · High speed communications interface protection system

Abstract

Working DS3/STS interface cards (18, 46) receive DS3 traffic on incoming DS3 communication lines (12, 42). The interface cards (18, 46) are operable to translate the DS3 signals into STS signals, and to "stuff" them into "A" and "B" clock frames provided to them by an "A" formatter (70) and a "B" formatter (74). These clock frames are then used to transmit data to the "A" formatter (70) and the "B" formatter (74). The DS3/STS interface cards (18,46) inspect incoming STS signals on "A" and "B" buses (82, 84) without having to switch to the inspected signal. Formatters 70 and 74 translate the STS data into formatted data, which eventually are transmitted in optical form on respective optical fibers (150, 190) at clock rates which do not have to be the same. Regeneration input and output ports ( 210, 216, 206, 166) allow the through-communication of telecommunications signals in STS format, obviating the need for down-translation to DS3 format and back-translation to STS format.

Claims8

Dependent claims

A high speed telecommunications interface protection system, comprising:

at least one interface circuit operable to receive a first signal in a first protocol and in response thereto to transmit a second signal in a second protocol, said interface circuit further operable to receive a third signal in said second protocol and in response thereto to transmit a fourth signal in said first protocol;
a first destination circuit coupled to said interface circuit, said first destination circuit operable to generate a first clock frame and to send said first clock frame to said interface circuit;
a second destination circuit coupled to said interface circuit, said second destination circuit operable to generate a second clock frame and to send said second clock frame to said interface circuit;
and
said interface circuit operable to transmit said second signal in said second protocol to said first destination circuit by inserting said second signal into said first clock frame to said first destination circuit, said interface circuit further operable to transmit said second signal in said second protocol to said second destination circuit by inserting said second signal into said second clock frame and retransmitting said second clock frame to said second destination circuit.

2 more elements

Dependencies are inferred from the claim text.

High speed communications interface protection system

Life of this patent

High speed communications interface protection system

Life of this patent

Abstract

Claims8