Phase locked loop synchronizer for a resampling system having incompatible input and output sample rates

A phase locked loop clock signal generation system comprising:

• a source of input video signal having a predetermined sample rate defined by an input clock signal and a horizontal line synchronizing signal component;
• signal conversion means, coupled to receive said input video signal and an output clock signal, for generating an output video signal having a horizontal line synchronizing signal component which has the same frequency as the horizontal line synchronizing signal component of the input video signal;
• phase comparison means, coupled to receive first and second signals representing the input clock signal and a signal representing the sampling phase of the output signal for generating an output signal representing a difference in sampling phase between said respective input and output signals;
• controlled oscillator means, responsive to the phase comparison means for generating said output clock signal which changes in frequency and phase to hold the output clock signal in a fixed phase relationship with the horizontal line synchronizing signal component of the input video signal.

A clock signal generation system suitable for use with a video signal conversion system that converts input video signals having a predetermined line scanning frequency into output video signals having the same predetermined line scanning frequency, said clock signal generation system comprising:

• controlled oscillator means, responsive to a control signal for generating said clock signal which may occupy a predetermined band of frequencies;
• phase comparison means, coupled to receive the input video signal and the output video signal for generating the control signal for the controlled oscillator means, said control signal representing a difference in phase between the respective line scanning frequencies of the input and output video signals;
• and
• means for applying the clock signal to the video signal conversion system to minimize the difference in phase between the respective line scanning frequencies of the input and output video signals.

A clock signal generation system suitable for use with a resampling system that interpolates a sampled data output signal, which is synchronous with an output clock signal, from a sampled data input signal which is synchronous with an input clock signal, the clock signal generation system comprising:

• controlled oscillator means, responsive to a control signal for generating the output clock signal;
• resampling control means, coupled to the resampling system, for determining instants at which samples of the output signal are generated from the input signal at a predetermined interpolation phase, to produce a phase reference signal having transitions which correspond to the determined instants;
• means, coupled to receive the sampled data output signal, for separating a synchronizing signal component therefrom and for providing said separated signal as an output synchronizing signal;
• phase comparison means, coupled to receive the input clock signal and the output synchronizing signal, for generating a phase difference signal representing a difference in phase between respective transitions of the output synchronizing signal and the input clock signal;
• means, coupled to the phase comparison means, and responsive to the phase difference signal for generating the control signal for the controlled oscillator means which operates to minimize the phase difference signal in magnitude;
• and
• means for applying the output clock signal to the resampling system to synchronize the interpolation of the output signal from the input signal.