US 5,335,018 A · Digital phase-locked loop

Abstract

A digital phase-locked loop (PLL) which responds to a square-wave input signal of on expected frequency f.sub.E and comprises a change-over switch which is switched in response to square-wave signals or different frequencies and precedes a main divider operating with a divisor D and which produces the output signal of the phase-locked loop. The change-over switch is activated as a function of the output signal and the input signal. In order to provide symmetrical locking in of the phase-locked loop and a small capture-and-hold range, the change-over switch is switched between a first square-wave signal of the frequency f.sub.1, a second square-wave signal of the second frequency f.sub.2 and a third square-wave signal of the frequency f.sub.3, in which: f.sub.1 .multidot.1/D=f.sub.E and k.multidot.f.sub.1 =f.sub.2 +(k-1).multidot.f.sub.3, A switching logic is provided which controls the change-over switch in such that it is switched to the signal of the first frequency f.sub.1 in the period between two pulses of the output signal, and to the signal of the second frequency f.sub.2 during a pulse of the output signal and a first state of the input signal, and to the signal of the third frequency f.sub.3 during a pulse of the output signal and a second state of the input signal. And f.sub.2 >f.sub.3 when the circuit locks in on the leading edges of the pulses of the input signal and f.sub.2 <f.sub.3 when the circuit locks in on the trailing edges.

Claims24

Dependent claims

A digital phase-locked loop (PLL) which responds to a square-wave input signal of expected frequency f.sub.E and comprises:

a change-over switch which is switched in response to square-wave signals of different frequencies and precedes a main divider operating with a divisor D, the main divider producing the output signal of the phase-locked loop, the change-over switch being activated via a switching logic dependent upon said output signal and the input signal, characterized in that
the change-over switch is switched between a first square-wave signal of a first frequency f.sub.1, a second square-wave signal of a second frequency f.sub.2 and a third square-wave signal of a third frequency f.sub.3, in which f.sub.1 (1/D)=F.sub.E, and the switching logic controls the change-over switch such that it is switched to the first signal of the first frequency f.sub.1 in the period between two pulses of the input signal, and to the second signal of the second frequency f.sub.2 during a pulse of the input signal and a first state of the output signal, and to the third signal of the third frequency f.sub.3 during a pulse of the input signal and a second state of the output signal, and in that f.sub.2 >f.sub.1 >f.sub.3 when the circuit locks in on the leading edges of the pulses of the input signal and f.sub.2 <f.sub.1 <f.sub.3 when the circuit locks in on the trailing edges.

A digital phase-locked loop comprising:

means for generating first, second and third square wave signals of different frequencies f.sub.1, f.sub.2, and f.sub.3, respectively,
switching means having input means for receiving said square-wave signals and an output,
a main frequency divider coupled between the output of the switching means and an output terminal of the phase-locked loop, and
switch control means having input means coupled to said output of the main frequency divider and to an input terminal which receives a square-wave input signal of a frequency f.sub.B, said switch control means being responsive to a square-wave output signal of the main frequency divider and to said square-wave input signal to supply a control signal to a control input of the switching means so that the switching means selectively passes said first, second and third square-wave signals to said main frequency divider as a function of said input signal and said output signal, said switch control means controlling the switching means so that the switching means passes the first square-wave signal of the frequency f.sub.1 in the period between two pulses of the output signal, the second square-wave signal of the frequency f.sub.2 being passed when the input and output square-wave signals are in opposite states and the third square-wave signal of the frequency f.sub.3 being passed when the input and output square-wave signals are in the same state, and wherein
f.sub.1 (1/D)=f.sub.E
and
k f.sub.1 =f.sub.2 +(k-1) f.sub.3
where D is the frequency divisor of the main frequency divider and k is a whole number between 1 and infinity.

5 more elements

Dependencies are inferred from the claim text.

Digital phase-locked loop

Life of this patent

Digital phase-locked loop

Life of this patent

Abstract

Claims24