# US 5,335,015 A · Method for improved dynamic range of BCMD image sensors

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- Number: US 5,335,015 A
- Document ID: US5335015A
- Status: Granted
- Kind: A
- Application number: 07/969,668
- Filed: 1992-10-30
- Granted: 1994-08-02
- Earliest claimed: 1992-10-30
- Assignees: Texas Instruments Incorporated
- Inventors: Alan N. Cooper; William P. McCracken; Jaroslav Hynecek
- Web page: https://patentgrep.com/patent/US5335015A

## CPC

- H04N 25/621: for the control of blooming
- H04N 25/76: Addressed sensors, e.g. MOS or CMOS sensors
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

The dynamic range of an image array photosite is improved by, first, turning on a column clamp transistor having a source coupled to a photosite transistor source and a drain coupled to a photosite transistor drain, wherein the column clamp transistor is turned on by a column clamp transistor gate voltage; then decreasing a current supplied to a column sense line below a quiescent value, wherein the column sense line is coupled to the photosite transistor source; then turning on the photosite transistor by a photosite transistor gate voltage; then turning off the photosite transistor and the column clamp transistor at substantially the same time; then increasing the current above the quiescent value; and then returning the current to the quiescent value.

## Claims

### Claim 1

A method for improving the dynamic range of an image array photosite, comprising the steps of:
turning on a column clamp transistor having a source coupled to a photosite transistor source and a drain coupled to a photosite transistor drain, said column clamp transistor is turned on by a column clamp transistor gate voltage;
decreasing a current supplied to a column sense line below a quiescent value, said column sense line is coupled to said photosite transistor source;
turning on said photosite transistor by a photosite transistor gate voltage;
turning off said photosite transistor and said column clamp transistor at substantially the same time;
increasing said current above said quiescent value; and
returning said current to said quiescent value.

### Claim 2 (depends on 1)

The method of claim 1 wherein said returning step is performed before a source voltage of said photosite transistor source exceeds zero volts relative to ground.

### Claim 3 (depends on 1)

The method of claim 1 wherein the current supplied to the column sense line is decreased by increasing a control voltage that controls the current, and the current is increased by lowering the control voltage.

### Claim 4 (depends on 3)

The method of claim 3 wherein the control voltage is provided by a digital implementation.

### Claim 5 (depends on 3)

The method of claim 3 wherein the control voltage is provided by an analog implementation.

### Claim 6 (depends on 5)

The method of claim 5 wherein the control voltage is generated by applying the column clamp transistor gate voltage through a capacitor.

### Claim 7 (depends on 1)

The method of claim 1 wherein the photosite transistor is a P-type buried channel MOS transistor.