# US 5,334,962 A · High-speed data supply pathway systems

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- Number: US 5,334,962 A
- Document ID: US5334962A
- Status: Granted
- Kind: A
- Application number: 07/530,461
- Filed: 1990-05-29
- Granted: 1994-08-02
- Earliest claimed: 1987-09-18
- Assignees: Q-Dot, Inc.
- Inventors: Brian P. Higgins; David W. Gardner; Kerry D. Rhea; Thomas E. Linnenbrink; Rebecca S. Reed; Peter C. T. Roberts
- Web page: https://patentgrep.com/patent/US5334962A

## CPC

- G11C 11/4097: Bit-line organisation, e.g. bit-line layout, folded bit lines
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The high speed data pathway system is used to convey data signals to integrated circuits connected to mother and daughter boards. The integrated circuits include a package and an integrated circuit chip carried by the package. An internal transmission line is carried by the package and coupled to the integrated circuit chip. The package includes both input and output connections for the internal transmission line. A high speed pathway is formed by serially connecting the internal transmission lines with external transmission lines to form a unified transmission medium. Advantageously, the internal transmission lines, external transmission lines and the connection between them have substantially corresponding characteristic impedances.

## Claims

### Claim 1

A very fast electrical data transmission pathway for connecting to at least one high speed integrated circuit comprising an integrated circuit chip carried by an integrated circuit package, said pathway comprising:
a plurality of differential transmission lines external to the integrated circuit package;
at least one continuous internal transmission line extending through said integrated circuit package;
means for connecting said integrated circuit chip to said internal transmission line; and
means for connecting said internal transmission line in electrical series with at least two of said plurality of differential transmission lines.

### Claim 2 (depends on 1)

A data pathway in accordance with claim 1 wherein said integrated circuit chip is a gallium arsenide passive receiver circuit.

### Claim 3 (depends on 1)

A data pathway in accordance with claim 1 wherein said integrated circuit chip is an active gallium arsenide tristate transceiver circuit.

### Claim 4 (depends on 1)

A data pathway in accordance with claim 1 wherein said differential transmission lines each comprise coaxial transmission means.

### Claim 5 (depends on 1)

A data pathway in accordance with claim 1 wherein said differential transmission lines are carried by a circuit board and said internal transmission line extends through said integrated circuit package between an input terminal and an output terminal thereof; and
said means for connecting said internal transmission line with said differential transmission lines comprises means for connecting the input terminal to one of said plurality of differential transmission lines at said circuit board and means for connecting the output terminal to another of said plurality of differential transmission lines at said circuit board.

### Claim 6 (depends on 5)

A data pathway in accordance with claim 5 wherein each of said plurality of differential transmission lines has a substantially equal characteristic impedance and said internal transmission line has an impedance substantially corresponding to the characteristic impedance of the differential transmission lines.

### Claim 7 (depends on 6)

A data pathway in accordance with claim 6 wherein the input terminal and the output terminal each have an impedance substantially corresponding to the characteristic impedance of the differential transmission lines.